update generation mechanism
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parent
b5d154c04d
commit
1ed351f199
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@ -78,9 +78,7 @@ if(ENABLE_CODEGEN AND EXISTS ${GENERATOR_JAR})
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list(APPEND ${CORE_NAME}_MAPPING -m "${TMPL_DIR}/CORENAME.cpp.gtl:${DBT_CORE_TGC_DIR}/src/iss/${CORE_NAMEL}.cpp")
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list(APPEND ${CORE_NAME}_MAPPING -m "${TMPL_DIR}/${BACKEND}/CORENAME.cpp.gtl:${DBT_CORE_TGC_DIR}/src/vm/interp/vm_${CORE_NAMEL}.cpp")
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list(APPEND ${CORE_NAME}_MAPPING -m "${TMPL_DIR}/CORENAME_instr.yaml.gtl:${DBT_CORE_TGC_DIR}/${CORE_NAME}_instr.yaml")
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if(NOT EXISTS ${DBT_CORE_TGC_DIR}/${CORE_NAME}_cycles.json)
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list(APPEND ${CORE_NAME}_MAPPING -m "${TMPL_DIR}/CORENAME_cyles.txt.gtl:${DBT_CORE_TGC_DIR}/${CORE_NAME}_cycles.json")
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endif()
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list(APPEND ${CORE_NAME}_MAPPING -m "${TMPL_DIR}/CORENAME_cyles.txt.gtl:${DBT_CORE_TGC_DIR}/${CORE_NAME}_cycles.json:no")
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set(${CORE_NAME}_OUTPUT_FILES ${DBT_CORE_TGC_DIR}/incl/iss/arch/${CORE_NAMEL}.h ${DBT_CORE_TGC_DIR}/src/iss/${CORE_NAMEL}.cpp ${DBT_CORE_TGC_DIR}/src/vm/interp/vm_${CORE_NAMEL}.cpp)
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#add_custom_command(
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2
coredsl
2
coredsl
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@ -1 +1 @@
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Subproject commit c5f57570bc03316b80ad2e6d3011222ded5fdbd8
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Subproject commit b7c415e0a785c91fd18a798ba88b5a8f91929510
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2
tgfs
2
tgfs
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@ -1 +1 @@
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Subproject commit ef2a4df925d621b3e57f5d10e61dbcc90b4e60cc
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Subproject commit 68b5697c8f1acb7c739bcb4454abce0c89379221
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