234 lines
9.7 KiB
C++
234 lines
9.7 KiB
C++
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#include "testbench.h"
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#include <factory.h>
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#include <tlm/scc/tlm_gp_shared.h>
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#undef CHECK
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#include <catch2/catch_all.hpp>
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#include <unordered_map>
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using namespace sc_core;
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factory::add<testbench> tb;
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bool is_equal(tlm::tlm_generic_payload const& a, tlm::tlm_generic_payload const& b) {
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auto ret = true;
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ret &= a.get_command() == b.get_command();
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ret &= a.get_address() == b.get_address();
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ret &= a.get_data_length() == b.get_data_length();
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for(auto i = 0u; i < a.get_data_length(); ++i)
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ret &= a.get_data_ptr()[i] == b.get_data_ptr()[i];
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// if(a.get_byte_enable_ptr() && b.get_byte_enable_ptr()) {
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// ret &= a.get_byte_enable_length() == b.get_byte_enable_length();
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// for(auto i=0u; i<a.get_byte_enable_length(); ++i)
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// ret &= a.get_byte_enable_ptr()[i] == b.get_byte_enable_ptr()[i];
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// }
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ret &= a.get_command() == b.get_command();
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// if(!ret) SCCWARN()<<"Comparison failed: "<<a<<" and "<<b;
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return ret;
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}
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template <typename bus_cfg>
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tlm::tlm_generic_payload* prepare_trans(uint64_t start_address, unsigned addr_incr, unsigned len, unsigned width, unsigned id) {
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auto trans = tlm::scc::tlm_mm<>::get().allocate<axi::axi4_extension>(len);
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trans->set_address(start_address);
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tlm::scc::setId(*trans, id);
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auto ext = trans->get_extension<axi::axi4_extension>();
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trans->set_data_length(len);
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trans->set_streaming_width(len);
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ext->set_size(scc::ilog2(width));
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sc_assert(len < (bus_cfg::BUSWIDTH / 8) || len % (bus_cfg::BUSWIDTH / 8) == 0);
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auto length = (len * 8 - 1) / (8 * width);
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if(width == (bus_cfg::BUSWIDTH / 8) && start_address % (bus_cfg::BUSWIDTH / 8))
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length++;
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ext->set_length(length);
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// ext->set_burst(len * 8 > bus_cfg::buswidth ? axi::burst_e::INCR : axi::burst_e::FIXED);
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ext->set_burst(axi::burst_e::INCR);
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ext->set_id(id);
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return trans;
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}
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inline void randomize(tlm::tlm_generic_payload& gp) {
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static uint8_t req_cnt{0};
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for(size_t i = 0; i < gp.get_data_length(); ++i) {
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*(gp.get_data_ptr() + i) = i % 2 ? i : req_cnt;
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}
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req_cnt++;
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}
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template <typename STATE> unsigned run_scenario(STATE& state) {
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auto& dut = factory::get<testbench>();
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dut.tgt_pe.set_operation_cb([&state](axi::axi_protocol_types::tlm_payload_type& trans) -> unsigned {
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auto id = axi::get_axi_id(trans);
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if(trans.is_read()) {
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for(size_t i = 0; i < trans.get_data_length(); ++i) {
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*(trans.get_data_ptr() + i) = i % 2 ? i : (state.resp_cnt + 128);
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}
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state.read_tx[id].second.emplace_back(&trans);
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}
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if(trans.is_write())
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state.write_tx[id].second.emplace_back(&trans);
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SCCDEBUG(__FUNCTION__) << "RX: " << trans;
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state.resp_cnt++;
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return 0;
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});
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dut.rst.write(false);
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sc_start(state.ResetCycles * dut.clk.period());
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dut.rst.write(true);
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sc_start(dut.clk.period());
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auto run1 = sc_spawn([&dut, &state]() {
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unsigned int StartAddr{0x0};
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for(int i = 0; i < state.NumberOfIterations; ++i) {
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tlm::scc::tlm_gp_shared_ptr trans =
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prepare_trans<testbench::bus_cfg>(StartAddr, 4, state.BurstLengthByte, state.BurstSizeBytes, 1);
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trans->set_command(tlm::TLM_READ_COMMAND);
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SCCDEBUG(__FUNCTION__) << "run1, iteration " << i << " TX: " << *trans;
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dut.intor_pe.transport(*trans, false);
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state.read_tx[axi::get_axi_id(*trans)].first.emplace_back(trans);
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StartAddr += state.BurstSizeBytes;
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}
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});
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auto run2 = sc_spawn([&dut, &state]() {
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unsigned int StartAddr{0x2000};
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for(int i = 0; i < state.NumberOfIterations; ++i) {
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tlm::scc::tlm_gp_shared_ptr trans =
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prepare_trans<testbench::bus_cfg>(StartAddr, 4, state.BurstLengthByte, state.BurstSizeBytes, 2);
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trans->set_command(tlm::TLM_WRITE_COMMAND);
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randomize(*trans);
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SCCDEBUG(__FUNCTION__) << "run2, iteration " << i << " TX: " << *trans;
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dut.intor_pe.transport(*trans, false);
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state.write_tx[axi::get_axi_id(*trans)].first.emplace_back(trans);
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StartAddr += state.BurstSizeBytes;
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}
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});
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auto run3 = sc_spawn([&dut, &state]() {
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unsigned int StartAddr{0x1000};
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for(int i = 0; i < state.NumberOfIterations; ++i) {
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tlm::scc::tlm_gp_shared_ptr trans =
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prepare_trans<testbench::bus_cfg>(StartAddr, 4, state.BurstLengthByte, state.BurstSizeBytes, 3);
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trans->set_command(tlm::TLM_READ_COMMAND);
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SCCDEBUG(__FUNCTION__) << "run3, iteration " << i << " TX: " << *trans;
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dut.intor_pe.transport(*trans, false);
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state.read_tx[axi::get_axi_id(*trans)].first.emplace_back(trans);
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StartAddr += state.BurstSizeBytes;
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}
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});
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auto run4 = sc_spawn([&dut, &state]() {
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unsigned int StartAddr{0x3000};
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for(int i = 0; i < state.NumberOfIterations; ++i) {
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tlm::scc::tlm_gp_shared_ptr trans =
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prepare_trans<testbench::bus_cfg>(StartAddr, 4, state.BurstLengthByte, state.BurstSizeBytes, 4);
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trans->set_command(tlm::TLM_WRITE_COMMAND);
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randomize(*trans);
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SCCDEBUG(__FUNCTION__) << "run4, iteration " << i << " TX: " << *trans;
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dut.intor_pe.transport(*trans, false);
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state.write_tx[axi::get_axi_id(*trans)].first.emplace_back(trans);
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StartAddr += state.BurstSizeBytes;
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}
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});
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unsigned cycles{0};
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while(cycles < 1000 && !(run1.terminated() && run2.terminated() && run3.terminated() && run4.terminated())) {
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sc_start(10 * dut.clk.period());
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cycles += 10;
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}
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return cycles;
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}
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void axi4_burst_alignment(bool pipelined_wrreq, bool write_bp) {
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struct {
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unsigned int ResetCycles{4};
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unsigned int BurstLengthByte{16};
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unsigned int BurstSizeBytes{8};
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unsigned int NumberOfIterations{8};
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std::unordered_map<unsigned, std::pair<std::vector<tlm::scc::tlm_gp_shared_ptr>, std::vector<tlm::scc::tlm_gp_shared_ptr>>> read_tx;
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std::unordered_map<unsigned, std::pair<std::vector<tlm::scc::tlm_gp_shared_ptr>, std::vector<tlm::scc::tlm_gp_shared_ptr>>>
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write_tx;
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unsigned resp_cnt{0};
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} state;
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auto& dut = factory::get<testbench>();
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dut.intor_bfm.pipelined_wrreq = pipelined_wrreq;
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dut.tgt_pe.wr_data_accept_delay.set_value(write_bp ? 1 : 0);
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auto cycles = run_scenario(state);
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REQUIRE(cycles < 1000);
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REQUIRE(sc_report_handler::get_count(SC_ERROR) == 0);
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REQUIRE(sc_report_handler::get_count(SC_WARNING) == 0);
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REQUIRE(state.resp_cnt == 4 * state.NumberOfIterations);
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for(auto& e : state.write_tx) {
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auto const& send_tx = e.second.first;
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auto const& recv_tx = e.second.second;
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REQUIRE(send_tx.size() == recv_tx.size());
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for(auto i = 0; i < send_tx.size(); ++i) {
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REQUIRE(send_tx[i]->get_response_status() == tlm::TLM_OK_RESPONSE);
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CHECK(is_equal(*send_tx[i], *recv_tx[i]));
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}
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}
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for(auto& e : state.read_tx) {
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auto const& send_tx = e.second.first;
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auto const& recv_tx = e.second.second;
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REQUIRE(send_tx.size() == recv_tx.size());
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for(auto i = 0; i < send_tx.size(); ++i) {
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REQUIRE(send_tx[i]->get_response_status() == tlm::TLM_OK_RESPONSE);
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CHECK(is_equal(*send_tx[i], *recv_tx[i]));
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}
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}
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}
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void axi4_narrow_burst(bool pipelined_wrreq, bool write_bp) {
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struct {
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unsigned int ResetCycles{4};
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unsigned int BurstLengthByte{16};
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unsigned int BurstSizeBytes{4};
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unsigned int NumberOfIterations{8};
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std::unordered_map<unsigned, std::pair<std::vector<tlm::scc::tlm_gp_shared_ptr>, std::vector<tlm::scc::tlm_gp_shared_ptr>>> read_tx;
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std::unordered_map<unsigned, std::pair<std::vector<tlm::scc::tlm_gp_shared_ptr>, std::vector<tlm::scc::tlm_gp_shared_ptr>>>
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write_tx;
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unsigned resp_cnt{0};
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} state;
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auto& dut = factory::get<testbench>();
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dut.intor_bfm.pipelined_wrreq = pipelined_wrreq;
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dut.tgt_pe.wr_data_accept_delay.set_value(write_bp ? 1 : 0);
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auto cycles = run_scenario(state);
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REQUIRE(cycles < 1000);
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REQUIRE(sc_report_handler::get_count(SC_ERROR) == 0);
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REQUIRE(sc_report_handler::get_count(SC_WARNING) == 0);
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REQUIRE(state.resp_cnt == 4 * state.NumberOfIterations);
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for(auto& e : state.write_tx) {
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auto const& send_tx = e.second.first;
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auto const& recv_tx = e.second.second;
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REQUIRE(send_tx.size() == recv_tx.size());
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for(auto i = 0; i < send_tx.size(); ++i)
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CHECK(is_equal(*send_tx[i], *recv_tx[i]));
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}
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for(auto& e : state.read_tx) {
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auto const& send_tx = e.second.first;
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auto const& recv_tx = e.second.second;
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REQUIRE(send_tx.size() == recv_tx.size());
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for(auto i = 0; i < send_tx.size(); ++i)
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CHECK(is_equal(*send_tx[i], *recv_tx[i]));
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}
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}
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TEST_CASE("axi4_burst_alignment", "[AXI][pin-level]") { axi4_burst_alignment(false, false); }
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TEST_CASE("axi4_narrow_burst", "[AXI][pin-level]") { axi4_narrow_burst(false, false); }
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TEST_CASE("axi4_burst_alignment_with_bp", "[AXI][pin-level]") { axi4_burst_alignment(false, true); }
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TEST_CASE("axi4_narrow_burst_with_bp", "[AXI][pin-level]") { axi4_narrow_burst(false, true); }
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TEST_CASE("axi4_burst_alignment_pipelined_write", "[AXI][pin-level]") { axi4_burst_alignment(true, false); }
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TEST_CASE("axi4_narrow_burst_pipelined_write", "[AXI][pin-level]") { axi4_narrow_burst(true, false); }
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TEST_CASE("axi4_burst_alignment_pipelined_write_with_bp", "[AXI][pin-level]") { axi4_burst_alignment(true, true); }
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TEST_CASE("axi4_narrow_burst_pipelined_write_with_bp", "[AXI][pin-level]") { axi4_narrow_burst(true, true); }
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