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updates ace_pin_level testcase with cacheline and scc

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Hongyu Liu
2023-10-05 15:36:33 +02:00
parent e30a569cfa
commit f83e61aa1f
3 changed files with 16 additions and 44 deletions
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tests/ace_pin_level/testbench.h
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@@ -16,7 +16,7 @@ using namespace axi::pe;
class testbench : public sc_core::sc_module
,public tlm::scc::pe::intor_bw_b {
public:
using bus_cfg = axi::ace_cfg</*BUSWIDTH=*/64, /*ADDRWIDTH=*/32, /*IDWIDTH=*/4, /*USERWIDTH=*/1>;
using bus_cfg = axi::ace_cfg</*BUSWIDTH=*/64, /*ADDRWIDTH=*/32, /*IDWIDTH=*/4, /*USERWIDTH=*/1,/*CACHELINE*/64>;
sc_core::sc_time clk_period{10, sc_core::SC_NS};
sc_core::sc_clock clk{"clk", clk_period, 0.5, sc_core::SC_ZERO_TIME, true};