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updates ace_pin_level testcase with cacheline and scc

This commit is contained in:
Hongyu Liu 2023-10-05 15:36:33 +02:00
parent e30a569cfa
commit f83e61aa1f
3 changed files with 16 additions and 44 deletions
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2
scc

@ -1 +1 @@
Subproject commit b205dce627b36cc865c9da372a2e84e927a5e12a
Subproject commit 77a9f223d7dc8cf838d95155f6023385bd6fdd03

56
tests/ace_pin_level/ace_narrow_burst_test.cpp
View File

@ -15,8 +15,9 @@ struct {
unsigned int BurstLengthByte{16};
// unsigned int BurstLengthByte{32};
unsigned int BurstSizeBytes{8};
// unsigned int NumberOfIterations{8};
unsigned int NumberOfIterations{2};
// unsigned int NumberOfIterations{8};
unsigned int NumberOfIterations{2};
unsigned int CachelineSizeBytes={64}; //
std::unordered_map<unsigned, std::pair<std::vector<tlm::scc::tlm_gp_shared_ptr>, std::vector<tlm::scc::tlm_gp_shared_ptr>>> read_tx;
std::unordered_map<unsigned, std::pair<std::vector<tlm::scc::tlm_gp_shared_ptr>, std::vector<tlm::scc::tlm_gp_shared_ptr>>> write_tx;
std::unordered_map<unsigned, std::pair<std::vector<tlm::scc::tlm_gp_shared_ptr>, std::vector<tlm::scc::tlm_gp_shared_ptr>>> snoop_tx;
@ -42,26 +43,6 @@ bool operator==(tlm::tlm_generic_payload const& a, tlm::tlm_generic_payload cons
return ret;
}
template<typename bus_cfg>
tlm::tlm_generic_payload* prepare_trans(uint64_t start_address, unsigned addr_incr, unsigned len, unsigned width, unsigned id) {
auto trans = tlm::scc::tlm_mm<>::get().allocate<axi::axi4_extension>(len);
trans->set_address(start_address);
tlm::scc::setId(*trans, id);
auto ext = trans->get_extension<axi::axi4_extension>();
trans->set_data_length(len);
trans->set_streaming_width(len);
ext->set_size(scc::ilog2(width));
sc_assert(len < (bus_cfg::BUSWIDTH / 8) || len % (bus_cfg::BUSWIDTH / 8) == 0);
auto length = (len * 8 - 1) / (8*width);
if(width==(bus_cfg::BUSWIDTH / 8) && start_address % (bus_cfg::BUSWIDTH / 8))
length++;
ext->set_length(length);
// ext->set_burst(len * 8 > bus_cfg::buswidth ? axi::burst_e::INCR : axi::burst_e::FIXED);
ext->set_burst(axi::burst_e::INCR);
ext->set_id(id);
return trans;
}
template<typename bus_cfg>
tlm::tlm_generic_payload* prepare_trans_ace(uint64_t start_address, unsigned addr_incr, unsigned len, unsigned width, unsigned id) {
auto trans = tlm::scc::tlm_mm<>::get().allocate<axi::ace_extension>(len);
@ -77,7 +58,10 @@ tlm::tlm_generic_payload* prepare_trans_ace(uint64_t start_address, unsigned add
length++;
ext->set_length(length);
// ext->set_burst(len * 8 > bus_cfg::buswidth ? axi::burst_e::INCR : axi::burst_e::FIXED);
ext->set_burst(axi::burst_e::INCR);
// here len is CachelineSizeBytes
// here burtst for read/write_trans and snoop_trans are different
ext->set_burst(axi::burst_e::INCR); //TBD???
//ext->set_burst(len*8 > bus_cfg::BUSWIDTH ? axi::burst_e::WRAP : axi::burst_e::INCR);
ext->set_id(id);
ext->set_snoop(axi::snoop_e::READ_SHARED); // set it so that is_data_less return true???
return trans;
@ -94,7 +78,7 @@ inline void randomize(tlm::tlm_generic_payload& gp) {
}
unsigned testbench::transport(tlm::tlm_generic_payload& trans) {
SCCDEBUG(__FUNCTION__)<<" update trans for snoop, with snoop_id = " << snoop_id;
SCCDEBUG(__FUNCTION__)<<" update snoop trans, with snoop_id = " << snoop_id;
// SCCDEBUG(__FUNCTION__)<<" in transport with trans " << trans;
// extracting address and snoop_e from ac_trans and pack them into cache data trans
auto ac_address = trans.get_address();
@ -102,9 +86,9 @@ unsigned testbench::transport(tlm::tlm_generic_payload& trans) {
auto ac_snoop=ext->get_snoop();
for(size_t i = 0; i < trans.get_data_length(); ++i) {
*(trans.get_data_ptr() + i) = i % 2 ? 123 : 128;
*(trans.get_data_ptr() + i) = i % 2 ? i : 128;
}
SCCDEBUG(__FUNCTION__)<<" vector size " <<state.snoop_tx[snoop_id].second.size();
//SCCDEBUG(__FUNCTION__)<<" vector size " <<state.snoop_tx[snoop_id].second.size();
state.snoop_tx[snoop_id].second.emplace_back(&trans);
/*
@ -195,11 +179,11 @@ unsigned run_scenario(STATE& state){
auto run5 = sc_spawn([&dut, &state](){
unsigned int StartAddr{0x0};
for(int i = 0; i < state.NumberOfIterations; ++i) {
// tlm::scc::tlm_gp_shared_ptr trans = prepare_trans<testbench::bus_cfg>(StartAddr, 4, state.BurstLengthByte, state.BurstSizeBytes, 1);
tlm::scc::tlm_gp_shared_ptr trans = prepare_trans_ace<testbench::bus_cfg>(StartAddr, 4, state.BurstLengthByte, state.BurstSizeBytes, 1);
tlm::scc::tlm_gp_shared_ptr trans = prepare_trans_ace<testbench::bus_cfg>(StartAddr, 4, state.CachelineSizeBytes, state.BurstSizeBytes, 5);
trans->set_command(tlm::TLM_READ_COMMAND);
SCCDEBUG(__FUNCTION__) << "run1, iteration " << i << "snoop_id = " << snoop_id <<" TX: "<<*trans;
dut.ace_tgt_pe.snoop(*trans);
SCCDEBUG(__FUNCTION__) << "run1, after iteration "<< i ;
state.snoop_tx[snoop_id].first.emplace_back(trans);
snoop_id++;
StartAddr += state.BurstSizeBytes;
@ -209,7 +193,7 @@ unsigned run_scenario(STATE& state){
unsigned cycles{0};
while(cycles<1000 && !(run1.terminated() && run2.terminated() && run3.terminated() && run4.terminated())){
// while(cycles<1000 && !(run1.terminated())){
// while(cycles<1000 && !(run5.terminated())){
sc_start(10 * dut.clk.period());
cycles+=10;
}
@ -221,7 +205,7 @@ TEST_CASE("ace_burst_alignment", "[AXI][pin-level]") {
state.resp_cnt=0;
auto cycles = run_scenario(state);
REQUIRE(cycles<1000);
// REQUIRE(cycles<1000);
REQUIRE(sc_report_handler::get_count(SC_ERROR) == 0);
REQUIRE(sc_report_handler::get_count(SC_WARNING) == 0);
@ -267,18 +251,6 @@ TEST_CASE("ace_burst_alignment", "[AXI][pin-level]") {
}
TEST_CASE("axi4_narrow_burst", "[AXI][pin-level]") {
/* struct {
unsigned int ResetCycles{4};
// unsigned int BurstLengthByte{32};
unsigned int BurstLengthByte{16};
unsigned int BurstSizeBytes{4};
// unsigned int NumberOfIterations{8};
unsigned int NumberOfIterations{1};
std::unordered_map<unsigned, std::pair<std::vector<tlm::scc::tlm_gp_shared_ptr>, std::vector<tlm::scc::tlm_gp_shared_ptr>>> read_tx;
std::unordered_map<unsigned, std::pair<std::vector<tlm::scc::tlm_gp_shared_ptr>, std::vector<tlm::scc::tlm_gp_shared_ptr>>> write_tx;
unsigned resp_cnt{0};
} state;
*/
state.resp_cnt=0;
auto cycles = run_scenario(state);

2
tests/ace_pin_level/testbench.h
View File

@ -16,7 +16,7 @@ using namespace axi::pe;
class testbench : public sc_core::sc_module
,public tlm::scc::pe::intor_bw_b {
public:
using bus_cfg = axi::ace_cfg</*BUSWIDTH=*/64, /*ADDRWIDTH=*/32, /*IDWIDTH=*/4, /*USERWIDTH=*/1>;
using bus_cfg = axi::ace_cfg</*BUSWIDTH=*/64, /*ADDRWIDTH=*/32, /*IDWIDTH=*/4, /*USERWIDTH=*/1,/*CACHELINE*/64>;
sc_core::sc_time clk_period{10, sc_core::SC_NS};
sc_core::sc_clock clk{"clk", clk_period, 0.5, sc_core::SC_ZERO_TIME, true};