SystemC/SystemC-Components-Test
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add modernizer fixits

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This commit is contained in:
Eyck Jentzsch
2020-05-27 16:47:07 +02:00
parent ae5ba9ca8e
commit f77b4d56e7
10 changed files with 75 additions and 52 deletions
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42
examples/transaction_recording/scv_tr_recording_example.cpp
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@@ -34,8 +34,8 @@ const unsigned ram_size = 256;
class rw_task_if : virtual public sc_interface {
public:
typedef sc_uint<8> addr_t;
typedef sc_uint<8> data_t;
using addr_t = sc_uint<8>;
using data_t = sc_uint<8>;
struct write_t {
addr_t addr;
data_t data;
@@ -73,7 +73,7 @@ public:
, bus_addr("bus_addr")
, data_rdy("data_rdy")
, bus_data("bus_data") {}
virtual void trace(sc_trace_file *tf) const;
void trace(sc_trace_file *tf) const override;
};
void pipelined_bus_ports::trace(sc_trace_file *tf) const {
@@ -111,10 +111,10 @@ public:
, read_gen("read", pipelined_stream, "addr", "data")
, write_gen("write", pipelined_stream, "addr", "data")
, addr_gen("addr", addr_stream, "addr")
, rdata_gen("rdata", data_stream, NULL, "data")
, rdata_gen("rdata", data_stream, nullptr, "data")
, wdata_gen("wdata", data_stream, "data") {}
virtual data_t read(const addr_t *p_addr);
virtual void write(const write_t *req);
data_t read(const addr_t *p_addr) override;
void write(const write_t *req) override;
};
rw_task_if::data_t rw_pipelined_transactor::read(const addr_t *addr) {
@@ -125,10 +125,10 @@ rw_task_if::data_t rw_pipelined_transactor::read(const addr_t *addr) {
wait(clk->posedge_event());
bus_addr = *addr;
rw = false;
addr_req = 1;
addr_req = true;
wait(addr_ack->posedge_event());
wait(clk->negedge_event());
addr_req = 0;
addr_req = false;
wait(addr_ack->negedge_event());
addr_gen.end_transaction(h1);
addr_phase.unlock();
@@ -153,10 +153,10 @@ void rw_pipelined_transactor::write(const write_t *req) {
wait(clk->posedge_event());
bus_addr = req->addr;
rw = true;
addr_req = 1;
addr_req = true;
wait(addr_ack->posedge_event());
wait(clk->negedge_event());
addr_req = 0;
addr_req = false;
wait(addr_ack->negedge_event());
addr_gen.end_transaction(h1);
addr_phase.unlock();
@@ -186,9 +186,9 @@ public:
class write_constraint : virtual public scv_constraint_base {
public:
scv_smart_ptr<rw_task_if::write_t> write;
SCV_CONSTRAINT_CTOR(write_constraint) {
SCV_CONSTRAINT(write->addr() <= ram_size);
SCV_CONSTRAINT(write->addr() != write->data());
SCV_CONSTRAINT_CTOR(write_constraint) { // NOLINT
SCV_CONSTRAINT(write->addr() <= ram_size); // NOLINT
SCV_CONSTRAINT(write->addr() != write->data()); // NOLINT
}
};
@@ -281,7 +281,7 @@ public:
};
inline void design::addr_phase() {
while (1) {
while (true) {
while (addr_req.read() != 1) {
wait(addr_req->value_changed_event());
}
@@ -293,9 +293,9 @@ inline void design::addr_phase() {
wait(clk->posedge_event());
}
addr_ack = 1;
addr_ack = true;
wait(clk->posedge_event());
addr_ack = 0;
addr_ack = false;
outstandingAddresses.push_back(_addr);
outstandingType.push_back(_rw);
@@ -304,7 +304,7 @@ inline void design::addr_phase() {
}
inline void design::data_phase() {
while (1) {
while (true) {
while (outstandingAddresses.empty()) {
wait(clk->posedge_event());
}
@@ -316,16 +316,16 @@ inline void design::data_phase() {
SCCINFO(sc_get_current_object()->name()) << "reading memory address " << outstandingAddresses.front() << " with value "
<< memory[outstandingAddresses.front().to_ulong()];
bus_data = memory[outstandingAddresses.front().to_ulong()];
data_rdy = 1;
data_rdy = true;
wait(clk->posedge_event());
data_rdy = 0;
data_rdy = false;
} else {
SCCINFO(sc_get_current_object()->name()) << "writing memory address " << outstandingAddresses.front() << " with value " << bus_data;
memory[outstandingAddresses.front().to_ulong()] = bus_data;
data_rdy = 1;
data_rdy = true;
wait(clk->posedge_event());
data_rdy = 0;
data_rdy = false;
}
outstandingAddresses.pop_front();
outstandingType.pop_front();