From f77b4d56e70208be8d9365ce9a4a2a6af0f38ce6 Mon Sep 17 00:00:00 2001 From: eyck Date: Wed, 27 May 2020 16:47:07 +0200 Subject: [PATCH] add modernizer fixits --- CMakeLists.txt | 19 +++++++++ examples/simple_system/gpio.cpp | 18 ++++---- examples/simple_system/plic.cpp | 10 ++--- examples/simple_system/spi.cpp | 2 +- examples/simple_system/test_initiator.cpp | 22 +++++----- examples/simple_system/uart.cpp | 2 +- .../scv_tr_recording_example.cpp | 42 +++++++++---------- sc-components | 2 +- tests/ordered_semaphore/sc_main.cpp | 2 +- tests/sim_performance/CMakeLists.txt | 8 ++++ 10 files changed, 75 insertions(+), 52 deletions(-) create mode 100644 tests/sim_performance/CMakeLists.txt diff --git a/CMakeLists.txt b/CMakeLists.txt index 0868b82..f6119f2 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -53,6 +53,25 @@ elseif ("${CMAKE_CXX_COMPILER_ID}" STREQUAL "MSVC") set(warnings "/W4 /WX /EHsc") endif() +if(ENABLE_COVERAGE) + include(CodeCoverage) + append_coverage_compiler_flags() + set(COVERAGE_EXCLUDES "osci-lib/scc/*" "/engr/dev/tools/*") +endif() + +find_program(CLANG_TIDY_EXE NAMES "clang-tidy-9") +if (CLANG_TIDY_EXE) + message(STATUS "clang-tidy found: ${CLANG_TIDY_EXE}") + set(CLANG_TIDY_CHECKS "-*,modernize-*,-modernize-use-trailing-return-type,clang-analyzer-core.*") + set(CMAKE_CXX_CLANG_TIDY + ${CLANG_TIDY_EXE}; + -checks=${CLANG_TIDY_CHECKS}; + -fix;) +else() + message(AUTHOR_WARNING "clang-tidy not found!") + set(CMAKE_CXX_CLANG_TIDY "" CACHE STRING "" FORCE) # delete it +endif() + setup_conan() # This line finds the boost lib and headers. diff --git a/examples/simple_system/gpio.cpp b/examples/simple_system/gpio.cpp index 041f505..3ce86ae 100644 --- a/examples/simple_system/gpio.cpp +++ b/examples/simple_system/gpio.cpp @@ -110,7 +110,7 @@ gpio::gpio(sc_module_name nm) regs->iof_sel.set_write_cb(update_pins_cb); } -gpio::~gpio() {} +gpio::~gpio() = default; void gpio::reset_cb() { if (rst_i.read()){ @@ -138,10 +138,10 @@ tlm::tlm_phase gpio::write_output(tlm::tlm_signal_gp& gp, size_t i, bool v void gpio::update_pins(uint32_t changed_bits) { sc_inout_rv<32>::data_type out_val; tlm::tlm_signal_gp gp; - bool val; + bool val{false}; for(size_t i=0, mask = 1; i<32; ++i, mask<<=1){ if(changed_bits&mask){ - if((regs->r_iof_en&mask!=0) && (iof0_i[i].size()==0 || iof1_i[i].size()==0)){ + if(((regs->r_iof_en&mask)!=0) && (iof0_i[i].size()==0 || iof1_i[i].size()==0)){ if((regs->r_iof_sel&mask)==0 && iof0_i[i].size()>0){ val=last_iof0[i]?sc_dt::Log_1:sc_dt::Log_0; } else if((regs->r_iof_sel&mask)==1 && iof1_i[i].size()>0) @@ -165,16 +165,12 @@ void gpio::pin_input(unsigned int tag, tlm::tlm_signal_gp& gp, sc_time& de delay=SC_ZERO_TIME; } auto mask = 1u<r_output_en&mask==0) + if((regs->r_output_en&mask)==0){ + if(gp.get_value()) regs->r_value|=mask; + else + regs->r_value&=~mask; forward_pin_input(tag, gp); - break; - case false: - if(regs->r_output_en&mask==0) regs->r_value&=~mask; - forward_pin_input(tag, gp); - break; } } diff --git a/examples/simple_system/plic.cpp b/examples/simple_system/plic.cpp index 58254c8..3b4cbac 100644 --- a/examples/simple_system/plic.cpp +++ b/examples/simple_system/plic.cpp @@ -71,7 +71,7 @@ plic::plic(sc_core::sc_module_name nm) sensitive << rst_i; } -plic::~plic() {} +plic::~plic() = default; void plic::init_callbacks() { m_claim_complete_write_cb = [=](scc::sc_register reg, uint32_t v) -> bool { @@ -130,7 +130,7 @@ void plic::handle_pending_int() { // identify high-prio pending interrupt and raise a core-interrupt uint32_t claim_int = 0; // claim interrupt uint32_t claim_prio = 0; // related priority (highest prio interrupt wins the race) - bool raise_int = 0; + bool raise_int = false; uint32_t thold = regs->r_threshold.threshold; // threshold value // todo: extend up to 255 bits (limited to 32 right now) @@ -146,7 +146,7 @@ void plic::handle_pending_int() { if (prio > claim_prio) { claim_prio = prio; claim_int = i; - raise_int = 1; + raise_int = true; SCCDEBUG("plic") << "pending interrupt activated: " << i; } } @@ -154,7 +154,7 @@ void plic::handle_pending_int() { if (raise_int) { regs->r_claim_complete = claim_int; - core_interrupt_o.write(1); + core_interrupt_o.write(true); // todo: evluate clock period } else { regs->r_claim_complete = 0; @@ -168,7 +168,7 @@ void plic::reset_pending_int(uint32_t irq) { SCCDEBUG("plic") << "reset pending interrupt: " << irq; // reset related pending bit regs->r_pending &= ~(0x1 << irq); - core_interrupt_o.write(0); + core_interrupt_o.write(false); // evaluate next pending interrupt handle_pending_int(); diff --git a/examples/simple_system/spi.cpp b/examples/simple_system/spi.cpp index 9553b32..94e0e5c 100644 --- a/examples/simple_system/spi.cpp +++ b/examples/simple_system/spi.cpp @@ -33,7 +33,7 @@ spi::spi(sc_core::sc_module_name nm) sensitive << rst_i; } -spi::~spi() {} +spi::~spi() {} // NOLINT void spi::clock_cb() { this->clk = clk_i.read(); } diff --git a/examples/simple_system/test_initiator.cpp b/examples/simple_system/test_initiator.cpp index 6f9fa59..c2effde 100644 --- a/examples/simple_system/test_initiator.cpp +++ b/examples/simple_system/test_initiator.cpp @@ -76,9 +76,9 @@ void test_initiator::test_unique_irq() { // -> no entry in pending reg // generate interrupt pulse (note: 1 is lowest usable register) - global_interrupts_o[2].write(1); + global_interrupts_o[2].write(true); wait(10_ns); - global_interrupts_o[2].write(0); + global_interrupts_o[2].write(false); wait(10_ns); reg_check(PLIC_PENDING_REG, 0x0); @@ -90,7 +90,7 @@ void test_initiator::test_unique_irq() { // -> pending bit change expected // -> core_interrupt expected - uint32_t v = read_bus(PLIC_PRIO1_REG); + read_bus(PLIC_PRIO1_REG); wait(10_ns); // enable single interrupt @@ -101,9 +101,9 @@ void test_initiator::test_unique_irq() { wait(10_ns); // generate interrupt pulse (note: 1 is lowest usable register) - global_interrupts_o[1].write(1); + global_interrupts_o[1].write(true); wait(10_ns); - global_interrupts_o[1].write(0); + global_interrupts_o[1].write(false); wait(10_ns); // read claim_complete register @@ -151,17 +151,17 @@ void test_initiator::test_parallel_irq() { wait(10_ns); // generate interrupt pulse (note: 1 is lowest usable register) - global_interrupts_o[1].write(1); + global_interrupts_o[1].write(true); wait(10_ns); - global_interrupts_o[1].write(0); + global_interrupts_o[1].write(false); wait(10_ns); - global_interrupts_o[2].write(1); + global_interrupts_o[2].write(true); wait(10_ns); - global_interrupts_o[2].write(0); + global_interrupts_o[2].write(false); wait(10_ns); - global_interrupts_o[3].write(1); + global_interrupts_o[3].write(true); wait(10_ns); - global_interrupts_o[3].write(0); + global_interrupts_o[3].write(false); wait(10_ns); // expect three pending registers diff --git a/examples/simple_system/uart.cpp b/examples/simple_system/uart.cpp index 864ecd2..e3f7995 100644 --- a/examples/simple_system/uart.cpp +++ b/examples/simple_system/uart.cpp @@ -33,7 +33,7 @@ uart::uart(sc_core::sc_module_name nm) sensitive << rst_i; } -uart::~uart() {} +uart::~uart() {} // NOLINT void uart::clock_cb() { this->clk = clk_i.read(); } diff --git a/examples/transaction_recording/scv_tr_recording_example.cpp b/examples/transaction_recording/scv_tr_recording_example.cpp index 57966be..7535acc 100644 --- a/examples/transaction_recording/scv_tr_recording_example.cpp +++ b/examples/transaction_recording/scv_tr_recording_example.cpp @@ -34,8 +34,8 @@ const unsigned ram_size = 256; class rw_task_if : virtual public sc_interface { public: - typedef sc_uint<8> addr_t; - typedef sc_uint<8> data_t; + using addr_t = sc_uint<8>; + using data_t = sc_uint<8>; struct write_t { addr_t addr; data_t data; @@ -73,7 +73,7 @@ public: , bus_addr("bus_addr") , data_rdy("data_rdy") , bus_data("bus_data") {} - virtual void trace(sc_trace_file *tf) const; + void trace(sc_trace_file *tf) const override; }; void pipelined_bus_ports::trace(sc_trace_file *tf) const { @@ -111,10 +111,10 @@ public: , read_gen("read", pipelined_stream, "addr", "data") , write_gen("write", pipelined_stream, "addr", "data") , addr_gen("addr", addr_stream, "addr") - , rdata_gen("rdata", data_stream, NULL, "data") + , rdata_gen("rdata", data_stream, nullptr, "data") , wdata_gen("wdata", data_stream, "data") {} - virtual data_t read(const addr_t *p_addr); - virtual void write(const write_t *req); + data_t read(const addr_t *p_addr) override; + void write(const write_t *req) override; }; rw_task_if::data_t rw_pipelined_transactor::read(const addr_t *addr) { @@ -125,10 +125,10 @@ rw_task_if::data_t rw_pipelined_transactor::read(const addr_t *addr) { wait(clk->posedge_event()); bus_addr = *addr; rw = false; - addr_req = 1; + addr_req = true; wait(addr_ack->posedge_event()); wait(clk->negedge_event()); - addr_req = 0; + addr_req = false; wait(addr_ack->negedge_event()); addr_gen.end_transaction(h1); addr_phase.unlock(); @@ -153,10 +153,10 @@ void rw_pipelined_transactor::write(const write_t *req) { wait(clk->posedge_event()); bus_addr = req->addr; rw = true; - addr_req = 1; + addr_req = true; wait(addr_ack->posedge_event()); wait(clk->negedge_event()); - addr_req = 0; + addr_req = false; wait(addr_ack->negedge_event()); addr_gen.end_transaction(h1); addr_phase.unlock(); @@ -186,9 +186,9 @@ public: class write_constraint : virtual public scv_constraint_base { public: scv_smart_ptr write; - SCV_CONSTRAINT_CTOR(write_constraint) { - SCV_CONSTRAINT(write->addr() <= ram_size); - SCV_CONSTRAINT(write->addr() != write->data()); + SCV_CONSTRAINT_CTOR(write_constraint) { // NOLINT + SCV_CONSTRAINT(write->addr() <= ram_size); // NOLINT + SCV_CONSTRAINT(write->addr() != write->data()); // NOLINT } }; @@ -281,7 +281,7 @@ public: }; inline void design::addr_phase() { - while (1) { + while (true) { while (addr_req.read() != 1) { wait(addr_req->value_changed_event()); } @@ -293,9 +293,9 @@ inline void design::addr_phase() { wait(clk->posedge_event()); } - addr_ack = 1; + addr_ack = true; wait(clk->posedge_event()); - addr_ack = 0; + addr_ack = false; outstandingAddresses.push_back(_addr); outstandingType.push_back(_rw); @@ -304,7 +304,7 @@ inline void design::addr_phase() { } inline void design::data_phase() { - while (1) { + while (true) { while (outstandingAddresses.empty()) { wait(clk->posedge_event()); } @@ -316,16 +316,16 @@ inline void design::data_phase() { SCCINFO(sc_get_current_object()->name()) << "reading memory address " << outstandingAddresses.front() << " with value " << memory[outstandingAddresses.front().to_ulong()]; bus_data = memory[outstandingAddresses.front().to_ulong()]; - data_rdy = 1; + data_rdy = true; wait(clk->posedge_event()); - data_rdy = 0; + data_rdy = false; } else { SCCINFO(sc_get_current_object()->name()) << "writing memory address " << outstandingAddresses.front() << " with value " << bus_data; memory[outstandingAddresses.front().to_ulong()] = bus_data; - data_rdy = 1; + data_rdy = true; wait(clk->posedge_event()); - data_rdy = 0; + data_rdy = false; } outstandingAddresses.pop_front(); outstandingType.pop_front(); diff --git a/sc-components b/sc-components index d3b67bc..71cab71 160000 --- a/sc-components +++ b/sc-components @@ -1 +1 @@ -Subproject commit d3b67bc32bf086321cd492d6d8f1aba30899699b +Subproject commit 71cab715b76935bf1559fcf6c1679997fd3ae9e9 diff --git a/tests/ordered_semaphore/sc_main.cpp b/tests/ordered_semaphore/sc_main.cpp index 242c4ae..a0d522b 100644 --- a/tests/ordered_semaphore/sc_main.cpp +++ b/tests/ordered_semaphore/sc_main.cpp @@ -41,7 +41,7 @@ public: SC_HAS_PROCESS(top); SC_THREAD(run); } - virtual ~top(){}; + ~top() override= default;; private: void run(){ sem.wait(); diff --git a/tests/sim_performance/CMakeLists.txt b/tests/sim_performance/CMakeLists.txt new file mode 100644 index 0000000..9bfb17d --- /dev/null +++ b/tests/sim_performance/CMakeLists.txt @@ -0,0 +1,8 @@ +cmake_minimum_required(VERSION 3.12) +add_executable (sim_performance + sc_main.cpp + blocks.cpp + top.cpp +) +target_link_libraries (sim_performance LINK_PUBLIC scc) +target_link_libraries (sim_performance LINK_PUBLIC ${Boost_LIBRARIES} )