SystemC/SystemC-Components-Test
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add modernizer fixits

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This commit is contained in:
Eyck Jentzsch
2020-05-27 16:47:07 +02:00
parent ae5ba9ca8e
commit f77b4d56e7
10 changed files with 75 additions and 52 deletions
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18
examples/simple_system/gpio.cpp
View File

@@ -110,7 +110,7 @@ gpio::gpio(sc_module_name nm)
regs->iof_sel.set_write_cb(update_pins_cb);
}
gpio::~gpio() {}
gpio::~gpio() = default;
void gpio::reset_cb() {
if (rst_i.read()){
@@ -138,10 +138,10 @@ tlm::tlm_phase gpio::write_output(tlm::tlm_signal_gp<bool>& gp, size_t i, bool v
void gpio::update_pins(uint32_t changed_bits) {
sc_inout_rv<32>::data_type out_val;
tlm::tlm_signal_gp<bool> gp;
bool val;
bool val{false};
for(size_t i=0, mask = 1; i<32; ++i, mask<<=1){
if(changed_bits&mask){
if((regs->r_iof_en&mask!=0) && (iof0_i[i].size()==0 || iof1_i[i].size()==0)){
if(((regs->r_iof_en&mask)!=0) && (iof0_i[i].size()==0 || iof1_i[i].size()==0)){
if((regs->r_iof_sel&mask)==0 && iof0_i[i].size()>0){
val=last_iof0[i]?sc_dt::Log_1:sc_dt::Log_0;
} else if((regs->r_iof_sel&mask)==1 && iof1_i[i].size()>0)
@@ -165,16 +165,12 @@ void gpio::pin_input(unsigned int tag, tlm::tlm_signal_gp<bool>& gp, sc_time& de
delay=SC_ZERO_TIME;
}
auto mask = 1u<<tag;
switch(gp.get_value()){
case true:
if(regs->r_output_en&mask==0)
if((regs->r_output_en&mask)==0){
if(gp.get_value())
regs->r_value|=mask;
else
regs->r_value&=~mask;
forward_pin_input(tag, gp);
break;
case false:
if(regs->r_output_en&mask==0) regs->r_value&=~mask;
forward_pin_input(tag, gp);
break;
}
}

10
examples/simple_system/plic.cpp
View File

@@ -71,7 +71,7 @@ plic::plic(sc_core::sc_module_name nm)
sensitive << rst_i;
}
plic::~plic() {}
plic::~plic() = default;
void plic::init_callbacks() {
m_claim_complete_write_cb = [=](scc::sc_register<uint32_t> reg, uint32_t v) -> bool {
@@ -130,7 +130,7 @@ void plic::handle_pending_int() {
// identify high-prio pending interrupt and raise a core-interrupt
uint32_t claim_int = 0; // claim interrupt
uint32_t claim_prio = 0; // related priority (highest prio interrupt wins the race)
bool raise_int = 0;
bool raise_int = false;
uint32_t thold = regs->r_threshold.threshold; // threshold value
// todo: extend up to 255 bits (limited to 32 right now)
@@ -146,7 +146,7 @@ void plic::handle_pending_int() {
if (prio > claim_prio) {
claim_prio = prio;
claim_int = i;
raise_int = 1;
raise_int = true;
SCCDEBUG("plic") << "pending interrupt activated: " << i;
}
}
@@ -154,7 +154,7 @@ void plic::handle_pending_int() {
if (raise_int) {
regs->r_claim_complete = claim_int;
core_interrupt_o.write(1);
core_interrupt_o.write(true);
// todo: evluate clock period
} else {
regs->r_claim_complete = 0;
@@ -168,7 +168,7 @@ void plic::reset_pending_int(uint32_t irq) {
SCCDEBUG("plic") << "reset pending interrupt: " << irq;
// reset related pending bit
regs->r_pending &= ~(0x1 << irq);
core_interrupt_o.write(0);
core_interrupt_o.write(false);
// evaluate next pending interrupt
handle_pending_int();

2
examples/simple_system/spi.cpp
View File

@@ -33,7 +33,7 @@ spi::spi(sc_core::sc_module_name nm)
sensitive << rst_i;
}
spi::~spi() {}
spi::~spi() {} // NOLINT
void spi::clock_cb() { this->clk = clk_i.read(); }

22
examples/simple_system/test_initiator.cpp
View File

@@ -76,9 +76,9 @@ void test_initiator::test_unique_irq() {
// -> no entry in pending reg
// generate interrupt pulse (note: 1 is lowest usable register)
global_interrupts_o[2].write(1);
global_interrupts_o[2].write(true);
wait(10_ns);
global_interrupts_o[2].write(0);
global_interrupts_o[2].write(false);
wait(10_ns);
reg_check(PLIC_PENDING_REG, 0x0);
@@ -90,7 +90,7 @@ void test_initiator::test_unique_irq() {
// -> pending bit change expected
// -> core_interrupt expected
uint32_t v = read_bus(PLIC_PRIO1_REG);
read_bus(PLIC_PRIO1_REG);
wait(10_ns);
// enable single interrupt
@@ -101,9 +101,9 @@ void test_initiator::test_unique_irq() {
wait(10_ns);
// generate interrupt pulse (note: 1 is lowest usable register)
global_interrupts_o[1].write(1);
global_interrupts_o[1].write(true);
wait(10_ns);
global_interrupts_o[1].write(0);
global_interrupts_o[1].write(false);
wait(10_ns);
// read claim_complete register
@@ -151,17 +151,17 @@ void test_initiator::test_parallel_irq() {
wait(10_ns);
// generate interrupt pulse (note: 1 is lowest usable register)
global_interrupts_o[1].write(1);
global_interrupts_o[1].write(true);
wait(10_ns);
global_interrupts_o[1].write(0);
global_interrupts_o[1].write(false);
wait(10_ns);
global_interrupts_o[2].write(1);
global_interrupts_o[2].write(true);
wait(10_ns);
global_interrupts_o[2].write(0);
global_interrupts_o[2].write(false);
wait(10_ns);
global_interrupts_o[3].write(1);
global_interrupts_o[3].write(true);
wait(10_ns);
global_interrupts_o[3].write(0);
global_interrupts_o[3].write(false);
wait(10_ns);
// expect three pending registers

2
examples/simple_system/uart.cpp
View File

@@ -33,7 +33,7 @@ uart::uart(sc_core::sc_module_name nm)
sensitive << rst_i;
}
uart::~uart() {}
uart::~uart() {} // NOLINT
void uart::clock_cb() { this->clk = clk_i.read(); }

42
examples/transaction_recording/scv_tr_recording_example.cpp
View File

@@ -34,8 +34,8 @@ const unsigned ram_size = 256;
class rw_task_if : virtual public sc_interface {
public:
typedef sc_uint<8> addr_t;
typedef sc_uint<8> data_t;
using addr_t = sc_uint<8>;
using data_t = sc_uint<8>;
struct write_t {
addr_t addr;
data_t data;
@@ -73,7 +73,7 @@ public:
, bus_addr("bus_addr")
, data_rdy("data_rdy")
, bus_data("bus_data") {}
virtual void trace(sc_trace_file *tf) const;
void trace(sc_trace_file *tf) const override;
};
void pipelined_bus_ports::trace(sc_trace_file *tf) const {
@@ -111,10 +111,10 @@ public:
, read_gen("read", pipelined_stream, "addr", "data")
, write_gen("write", pipelined_stream, "addr", "data")
, addr_gen("addr", addr_stream, "addr")
, rdata_gen("rdata", data_stream, NULL, "data")
, rdata_gen("rdata", data_stream, nullptr, "data")
, wdata_gen("wdata", data_stream, "data") {}
virtual data_t read(const addr_t *p_addr);
virtual void write(const write_t *req);
data_t read(const addr_t *p_addr) override;
void write(const write_t *req) override;
};
rw_task_if::data_t rw_pipelined_transactor::read(const addr_t *addr) {
@@ -125,10 +125,10 @@ rw_task_if::data_t rw_pipelined_transactor::read(const addr_t *addr) {
wait(clk->posedge_event());
bus_addr = *addr;
rw = false;
addr_req = 1;
addr_req = true;
wait(addr_ack->posedge_event());
wait(clk->negedge_event());
addr_req = 0;
addr_req = false;
wait(addr_ack->negedge_event());
addr_gen.end_transaction(h1);
addr_phase.unlock();
@@ -153,10 +153,10 @@ void rw_pipelined_transactor::write(const write_t *req) {
wait(clk->posedge_event());
bus_addr = req->addr;
rw = true;
addr_req = 1;
addr_req = true;
wait(addr_ack->posedge_event());
wait(clk->negedge_event());
addr_req = 0;
addr_req = false;
wait(addr_ack->negedge_event());
addr_gen.end_transaction(h1);
addr_phase.unlock();
@@ -186,9 +186,9 @@ public:
class write_constraint : virtual public scv_constraint_base {
public:
scv_smart_ptr<rw_task_if::write_t> write;
SCV_CONSTRAINT_CTOR(write_constraint) {
SCV_CONSTRAINT(write->addr() <= ram_size);
SCV_CONSTRAINT(write->addr() != write->data());
SCV_CONSTRAINT_CTOR(write_constraint) { // NOLINT
SCV_CONSTRAINT(write->addr() <= ram_size); // NOLINT
SCV_CONSTRAINT(write->addr() != write->data()); // NOLINT
}
};
@@ -281,7 +281,7 @@ public:
};
inline void design::addr_phase() {
while (1) {
while (true) {
while (addr_req.read() != 1) {
wait(addr_req->value_changed_event());
}
@@ -293,9 +293,9 @@ inline void design::addr_phase() {
wait(clk->posedge_event());
}
addr_ack = 1;
addr_ack = true;
wait(clk->posedge_event());
addr_ack = 0;
addr_ack = false;
outstandingAddresses.push_back(_addr);
outstandingType.push_back(_rw);
@@ -304,7 +304,7 @@ inline void design::addr_phase() {
}
inline void design::data_phase() {
while (1) {
while (true) {
while (outstandingAddresses.empty()) {
wait(clk->posedge_event());
}
@@ -316,16 +316,16 @@ inline void design::data_phase() {
SCCINFO(sc_get_current_object()->name()) << "reading memory address " << outstandingAddresses.front() << " with value "
<< memory[outstandingAddresses.front().to_ulong()];
bus_data = memory[outstandingAddresses.front().to_ulong()];
data_rdy = 1;
data_rdy = true;
wait(clk->posedge_event());
data_rdy = 0;
data_rdy = false;
} else {
SCCINFO(sc_get_current_object()->name()) << "writing memory address " << outstandingAddresses.front() << " with value " << bus_data;
memory[outstandingAddresses.front().to_ulong()] = bus_data;
data_rdy = 1;
data_rdy = true;
wait(clk->posedge_event());
data_rdy = 0;
data_rdy = false;
}
outstandingAddresses.pop_front();
outstandingType.pop_front();