first draft version of PLIC
This commit is contained in:
Soeren Jung
parent
4b25eb0b29
commit
f2fc62fbb8
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@ -1,11 +1,26 @@
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/*******************************************************************************
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* Copyright 2017 eyck@minres.com
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*
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* Licensed under the Apache License, Version 2.0 (the "License"); you may not
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* use this file except in compliance with the License. You may obtain a copy
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* of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations under
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* the License.
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******************************************************************************/
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#ifndef _E300_PLAT_MAP_H_
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#define _E300_PLAT_MAP_H_
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// need double braces, see https://stackoverflow.com/questions/6893700/how-to-construct-stdarray-object-with-initializer-list#6894191
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const std::array<sysc::target_memory_map_entry<32>, 4> e300_plat_map = {{
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{&i_plic, 0xc000000, 0x1000},
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{&i_plic, 0x0c000000, 0x200008},
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{&i_gpio, 0x10012000, 0x1000},
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{&i_uart, 0x10013000, 0x1000},
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{&i_spi, 0x10014000, 0x1000},
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{&i_spi, 0x10014000, 0x1000},
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}};
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#endif /* _E300_PLAT_MAP_H_ */
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@ -47,7 +47,7 @@ class plic_regs :
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public sc_core::sc_module,
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public sysc::resetable
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{
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protected:
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public:
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// storage declarations
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BEGIN_BF_DECL(priority_t, uint32_t);
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BF_FIELD(priority, 0, 3);
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@ -71,7 +71,6 @@ protected:
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sysc::sc_register<threshold_t> threshold;
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sysc::sc_register<uint32_t> claim_complete;
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public:
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plic_regs(sc_core::sc_module_name nm);
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template<unsigned BUSWIDTH=32>
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@ -97,8 +96,8 @@ inline void sysc::plic_regs::registerResources(sysc::tlm_target<BUSWIDTH>& targe
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target.addResource(priority, 0x4UL);
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target.addResource(pending, 0x1000UL);
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target.addResource(enabled, 0x2000UL);
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target.addResource(threshold, 0xc200000UL);
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target.addResource(claim_complete, 0xc200004UL);
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target.addResource(threshold, 0x00200000UL);
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target.addResource(claim_complete, 0x00200004UL);
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}
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#endif // _PLIC_REGS_H_
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@ -1,22 +1,45 @@
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////////////////////////////////////////////////////////////////////////////////
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// Copyright 2017 eyck@minres.com
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//
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// Licensed under the Apache License, Version 2.0 (the "License"); you may not
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// use this file except in compliance with the License. You may obtain a copy
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// of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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// License for the specific language governing permissions and limitations under
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// the License.
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// Copyright (C) 2017, MINRES Technologies GmbH
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// 1. Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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//
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// 2. Redistributions in binary form must reproduce the above copyright notice,
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// this list of conditions and the following disclaimer in the documentation
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// and/or other materials provided with the distribution.
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//
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// 3. Neither the name of the copyright holder nor the names of its contributors
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// may be used to endorse or promote products derived from this software
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// without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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// CONTRACT, STRICT LIABILITY0x200004, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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// POSSIBILITY OF SUCH DAMAGE.
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//
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// Contributors:
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// eyck@minres.com - initial API and implementation
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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// todo: truncate values beyond 7 (in prio_threshold write_cb)
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#include "plic.h"
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#include "gen/plic_regs.h"
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#include "sysc/utilities.h"
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#include <sysc/report.h>
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namespace sysc {
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@ -25,27 +48,146 @@ plic::plic(sc_core::sc_module_name nm)
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, tlm_target<>(clk)
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, NAMED(clk_i)
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, NAMED(rst_i)
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, NAMED(global_interrupts_i, 256)
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, NAMED(core_interrupt_o)
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, NAMEDD(plic_regs, regs)
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{
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regs->registerResources(*this);
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// register callbacks
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init_callbacks();
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regs->claim_complete.set_write_cb(m_claim_complete_write_cb);
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// port callbacks
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SC_METHOD(global_int_port_cb);
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for(uint8_t i = 0; i<255; i++) {
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sensitive << global_interrupts_i[i].pos();
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}
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dont_initialize();
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// register event callbacks
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SC_METHOD(clock_cb);
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sensitive<<clk_i;
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SC_METHOD(reset_cb);
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sensitive<<rst_i;
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}
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plic::~plic() {
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}
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void plic::clock_cb() {
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void plic::init_callbacks()
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{
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m_claim_complete_write_cb = [=](sysc::sc_register<uint32_t> reg, uint32_t v)->bool {
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reg.put(v);
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reset_pending_int(v);
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// std::cout << "Value of register: 0x" << std::hex << reg << std::endl;
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// todo: reset related interrupt and find next high-prio interrupt
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return true;
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};
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}
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void plic::clock_cb()
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{
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this->clk=clk_i.read();
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}
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void plic::reset_cb() {
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void plic::reset_cb()
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{
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if(rst_i.read())
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regs->reset_start();
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else
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regs->reset_stop();
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}
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// Functional handling of interrupts:
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// - global_int_port_cb()
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// - set pending register bits
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// - called by: incoming global_int
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// - handle_pending_int()
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// - update claim register content
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// - generate core-interrupt pulse
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// - called by:
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// - incoming global_int
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// - complete-register write access
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// - reset_pending_int(int-id)
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// - reset pending bit
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// - call next handle_pending_int()
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// - called by:
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// - complete-reg write register content
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void plic::global_int_port_cb()
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{
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// set related pending bit if enable is set for incoming global_interrupt
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// todo: extend up to 255 bits (limited to 32 right now)
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for(uint32_t i = 1; i<32; i++) {
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uint32_t enable_bits = regs->r_enabled;
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bool enable = enable_bits & (0x1 << i); // read enable bit
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if ( enable && global_interrupts_i[i].read() == 1 ) {
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regs->r_pending = regs->r_pending | ( 0x1 << i);
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LOG(logging::INFO) << "pending interrupt identified: " << i;
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}
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}
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handle_pending_int();
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}
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void plic::handle_pending_int()
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{
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// identify high-prio pending interrupt and raise a core-interrupt
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uint32_t claim_int = 0; // claim interrupt
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uint32_t claim_prio = 0; // related priority (highest prio interrupt wins the race)
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bool raise_int = 0;
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uint32_t thold = regs->r_threshold.threshold; // threshold value
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// todo: extend up to 255 bits (limited to 32 right now)
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for(uint32_t i = 1; i<32; i++) {
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uint32_t pending_bits = regs->r_pending;
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bool pending = (pending_bits & (0x1 << i)) ? true : false;
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uint32_t prio = regs->r_priority[i-1].priority; // read priority value
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if ( pending && thold < prio )
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{
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regs->r_pending = regs->r_pending | ( 0x1 << i);
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// below condition ensures implicitly that lowest id is selected in case of multiple identical priority-interrupts
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if ( prio > claim_prio ) {
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claim_prio = prio;
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claim_int = i;
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raise_int = 1;
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LOG(logging::INFO) << "pending interrupt activated: " << i;
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}
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}
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}
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if ( raise_int ) {
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regs->r_claim_complete = claim_int;
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core_interrupt_o.write(1);
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// todo: evluate clock period
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} else {
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regs->r_claim_complete = 0;
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LOG(logging::INFO) << "no further pending interrupt.";
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}
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}
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void plic::reset_pending_int(uint32_t irq)
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{
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// todo: evaluate enable register (see spec)
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// todo: make sure that pending is set, otherwise don't reset irq ... read spec.
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LOG(logging::INFO) << "reset pending interrupt: " << irq;
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// reset related pending bit
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regs->r_pending &= ~(0x1 << irq);
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core_interrupt_o.write(0);
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// evaluate next pending interrupt
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handle_pending_int();
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}
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} /* namespace sysc */
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@ -18,6 +18,7 @@
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#define _PLIC_H_
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#include <sysc/tlm_target.h>
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#include <sysc/register.h>
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namespace sysc {
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@ -26,15 +27,28 @@ class plic_regs;
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class plic: public sc_core::sc_module, public tlm_target<> {
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public:
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SC_HAS_PROCESS(plic);
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sc_core::sc_in<sc_core::sc_time> clk_i;
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sc_core::sc_in<bool> rst_i;
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sc_core::sc_in<sc_core::sc_time> clk_i;
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sc_core::sc_in<bool> rst_i;
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sc_core::sc_vector<sc_core::sc_in<bool>> global_interrupts_i;
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sc_core::sc_out<bool> core_interrupt_o;
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sc_core::sc_event raise_int_ev;
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sc_core::sc_event clear_int_ev;
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plic(sc_core::sc_module_name nm);
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virtual ~plic();
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protected:
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void clock_cb();
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void reset_cb();
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void init_callbacks();
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void global_int_port_cb();
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void handle_pending_int();
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void reset_pending_int(uint32_t irq);
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void raise_core_interrupt();
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void clear_core_interrupt();
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sc_core::sc_time clk;
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std::unique_ptr<plic_regs> regs;
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std::function<bool(sc_register<uint32_t>,uint32_t)> m_claim_complete_write_cb;
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};
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} /* namespace sysc */
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@ -89,7 +89,7 @@ int sc_main(int argc, char* argv[]){
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if(!sc_core::sc_end_of_simulation_invoked()) {
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LOG(logging::ERROR) << "simulation timed out";
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sc_stop();
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sc_core::sc_stop();
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}
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return 0;
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}
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@ -34,14 +34,21 @@ simple_system::simple_system(sc_core::sc_module_name nm)
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, NAMED(i_plic)
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, NAMED(s_clk)
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, NAMED(s_rst)
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, NAMED(s_global_interrupts, 256)
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, NAMED(s_core_interrupt)
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{
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// todo: discuss naming conventions (s_<signal> vs. <port>_i/_o) --> covnert into _s
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// bus connections
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i_master.intor(i_router.target[0]);
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size_t i=0;
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for(const auto& e: e300_plat_map){
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i_router.initiator.at(i)(e.target->socket);
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i_router.initiator[i](e.target->socket);
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i_router.add_target_range(i, e.start, e.size);
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i++;
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}
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// clock/reset connections
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i_uart.clk_i(s_clk);
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i_spi.clk_i(s_clk);
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i_gpio.clk_i(s_clk);
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@ -54,6 +61,12 @@ simple_system::simple_system(sc_core::sc_module_name nm)
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i_plic.rst_i(s_rst);
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i_master.rst_i(s_rst);
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// interrupt connections
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i_plic.core_interrupt_o(s_core_interrupt);
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i_plic.global_interrupts_i.bind(s_global_interrupts);
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i_master.global_interrupts_o(s_global_interrupts);
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i_master.core_interrupt_i(s_core_interrupt);
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SC_THREAD(gen_reset);
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}
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@ -48,6 +48,8 @@ public:
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plic i_plic;
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sc_core::sc_signal<sc_core::sc_time> s_clk;
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sc_core::sc_signal<bool> s_rst;
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sc_core::sc_vector<sc_core::sc_signal<bool>> s_global_interrupts;
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sc_core::sc_signal<bool> s_core_interrupt;
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simple_system(sc_core::sc_module_name nm);
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protected:
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@ -21,43 +21,266 @@
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*/
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#include "test_initiator.h"
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#include <sr_report/sr_report.h>
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#include <sysc/report.h>
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#include <sysc/utilities.h>
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#include <array>
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namespace sysc {
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// todo: move into gen folder somewhere (adapt code-generator)
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#define PLIC_PRIO1_REG 0x0C000004
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#define PLIC_PRIO2_REG 0x0C000008
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#define PLIC_PRIO3_REG 0x0C00000C
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#define PLIC_PRIO4_REG 0x0C000010
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#define PLIC_PENDING_REG 0x0C001000
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#define PLIC_ENABLE_REG 0x0C002000
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#define PLIC_PRIO_TRESHOLD_REG 0x0C200000
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#define PLIC_CLAIM_COMPLETE_REG 0x0C200004
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namespace sysc {
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test_initiator::test_initiator(sc_core::sc_module_name nm)
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: sc_core::sc_module(nm)
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, NAMED(intor)
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, NAMED(rst_i)
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, NAMED(global_interrupts_o, 256)
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, NAMED(core_interrupt_i)
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{
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SC_THREAD(run);
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SC_THREAD(run);
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SC_METHOD(core_irq_handler);
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sensitive << core_interrupt_i;
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dont_initialize();
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}
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void test_initiator::run() {
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void test_initiator::run()
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{
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// wait for reset
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if(rst_i.read()==false) wait(rst_i.posedge_event());
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wait(rst_i.negedge_event());
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wait(10_ns);
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// apply test-sequences
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test_unique_irq();
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test_frequent_irq();
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test_parallel_irq();
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test_irq_stress();
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// todo: review irq sequences from FW point of view ... expected ???
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}
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void test_initiator::test_unique_irq()
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{
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//// enable reg is not set
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// -> irq to be ignored
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// -> no core_interrupt
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// -> no entry in pending reg
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// generate interrupt pulse (note: 1 is lowest usable register)
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global_interrupts_o[2].write(1);
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wait(10_ns);
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global_interrupts_o[2].write(0);
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wait(10_ns);
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reg_check(PLIC_PENDING_REG, 0x0);
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wait(10_ns);
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reg_check(PLIC_CLAIM_COMPLETE_REG, 0x0);
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wait(10_ns);
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//// enable reg is set, then
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// -> pending bit change expected
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// -> core_interrupt expected
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uint32_t v = read_bus(PLIC_PRIO1_REG);
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wait(10_ns);
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// enable single interrupt
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write_bus(PLIC_PRIO1_REG, 0x1);
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wait(10_ns);
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write_bus(PLIC_ENABLE_REG, 0x2);
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wait(10_ns);
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// generate interrupt pulse (note: 1 is lowest usable register)
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global_interrupts_o[1].write(1);
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wait(10_ns);
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global_interrupts_o[1].write(0);
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wait(10_ns);
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// read claim_complete register
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reg_check(PLIC_PENDING_REG, 0x2);
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wait(10_ns);
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reg_check(PLIC_CLAIM_COMPLETE_REG, 0x1);
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wait(10_ns);
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//// after writing to claim_complete reg (per fw)
|
||||
// -> pending bit expected to be unset
|
||||
// -> enable bit expected to be set ... test with / without enable being set
|
||||
write_bus(PLIC_CLAIM_COMPLETE_REG, 0x1);
|
||||
wait(10_ns);
|
||||
reg_check(PLIC_PENDING_REG, 0x0);
|
||||
wait(10_ns);
|
||||
reg_check(PLIC_CLAIM_COMPLETE_REG, 0x0);
|
||||
wait(10_ns);
|
||||
|
||||
// todo: remove wait statements once the tlm_initiator is in place
|
||||
// todo: evaluate error messages ... provide correct pass/fail verdict
|
||||
|
||||
wait(100_ns);
|
||||
|
||||
}
|
||||
|
||||
void test_initiator::test_frequent_irq()
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
void test_initiator::test_parallel_irq()
|
||||
{
|
||||
|
||||
//// create three parallel global_int requests
|
||||
// -> read and clear bits one after the other
|
||||
// -> different priorities applied (reverse order)
|
||||
// -> correct priority handing expected
|
||||
// -> three core interrupts expected in total
|
||||
|
||||
|
||||
// reverse order priority configuration
|
||||
write_bus(PLIC_PRIO1_REG, 0x3);
|
||||
wait(10_ns);
|
||||
write_bus(PLIC_PRIO2_REG, 0x2);
|
||||
wait(10_ns);
|
||||
write_bus(PLIC_PRIO3_REG, 0x1);
|
||||
wait(10_ns);
|
||||
|
||||
// enable all three interrupts
|
||||
write_bus(PLIC_ENABLE_REG, 0xE);
|
||||
wait(10_ns);
|
||||
|
||||
// generate interrupt pulse (note: 1 is lowest usable register)
|
||||
global_interrupts_o[1].write(1);
|
||||
wait(10_ns);
|
||||
global_interrupts_o[1].write(0);
|
||||
wait(10_ns);
|
||||
global_interrupts_o[2].write(1);
|
||||
wait(10_ns);
|
||||
global_interrupts_o[2].write(0);
|
||||
wait(10_ns);
|
||||
global_interrupts_o[3].write(1);
|
||||
wait(10_ns);
|
||||
global_interrupts_o[3].write(0);
|
||||
wait(10_ns);
|
||||
|
||||
// expect three pending registers
|
||||
reg_check(PLIC_PENDING_REG, 0xE);
|
||||
wait(10_ns);
|
||||
|
||||
// expect lowest interrupt id to be highest int
|
||||
reg_check(PLIC_CLAIM_COMPLETE_REG, 0x1);
|
||||
wait(10_ns);
|
||||
|
||||
//// after writing to claim_complete reg (per fw)
|
||||
// -> next int to become highest irq
|
||||
write_bus(PLIC_CLAIM_COMPLETE_REG, 0x1);
|
||||
wait(10_ns);
|
||||
reg_check(PLIC_PENDING_REG, 0xC);
|
||||
wait(10_ns);
|
||||
reg_check(PLIC_CLAIM_COMPLETE_REG, 0x2);
|
||||
wait(10_ns);
|
||||
|
||||
//// after writing to claim_complete reg again (per fw)
|
||||
// -> next int to become highest irq
|
||||
write_bus(PLIC_CLAIM_COMPLETE_REG, 0x2);
|
||||
wait(10_ns);
|
||||
reg_check(PLIC_PENDING_REG, 0x8);
|
||||
wait(10_ns);
|
||||
reg_check(PLIC_CLAIM_COMPLETE_REG, 0x3);
|
||||
wait(10_ns);
|
||||
|
||||
//// after last writing to claim_complete reg again (per fw)
|
||||
// -> no further pending irq expected
|
||||
write_bus(PLIC_CLAIM_COMPLETE_REG, 0x3);
|
||||
wait(10_ns);
|
||||
reg_check(PLIC_PENDING_REG, 0x0);
|
||||
wait(10_ns);
|
||||
reg_check(PLIC_CLAIM_COMPLETE_REG, 0x0);
|
||||
wait(10_ns);
|
||||
|
||||
|
||||
// todo: advance upon register-write access ... remove above 10_ns waits
|
||||
// todo: evaluate error messages ... provide correct pass/fail verdict
|
||||
|
||||
wait(100_ns);
|
||||
|
||||
}
|
||||
|
||||
void test_initiator::test_irq_stress()
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
void test_initiator::write_bus(std::uint32_t adr, std::uint32_t dat)
|
||||
{
|
||||
tlm::tlm_generic_payload gp;
|
||||
std::array<uint8_t, 4> data;
|
||||
srInfo()("group", "comm")("read access");
|
||||
gp.set_command(tlm::TLM_READ_COMMAND);
|
||||
// gp.set_address(0x10012000);
|
||||
gp.set_address(0xc000004);
|
||||
data[3] = 0xff & dat>>24;
|
||||
data[2] = 0xff & dat>>16;
|
||||
data[1] = 0xff & dat>>8;
|
||||
data[0] = 0xff & dat;
|
||||
|
||||
LOG(logging::INFO) << "write_bus(0x" << std::hex << adr << ") : " << dat;
|
||||
|
||||
gp.set_command(tlm::TLM_WRITE_COMMAND);
|
||||
gp.set_address(adr);
|
||||
gp.set_data_ptr(data.data());
|
||||
gp.set_data_length(data.size());
|
||||
gp.set_streaming_width(4);
|
||||
sc_core::sc_time delay;
|
||||
intor->b_transport(gp, delay);
|
||||
wait(10_ns);
|
||||
srWarn()("group", "comm")("write access");
|
||||
gp.set_command(tlm::TLM_WRITE_COMMAND);
|
||||
gp.set_address(0x10012000);
|
||||
data[0]=0xA5;
|
||||
|
||||
if ( gp.get_response_status() != tlm::TLM_OK_RESPONSE ) {
|
||||
throw std::exception();
|
||||
}
|
||||
}
|
||||
|
||||
std::uint32_t test_initiator::read_bus(std::uint32_t adr)
|
||||
{
|
||||
|
||||
tlm::tlm_generic_payload gp;
|
||||
std::array<uint8_t, 4> data;
|
||||
|
||||
gp.set_command(tlm::TLM_READ_COMMAND);
|
||||
gp.set_address(adr);
|
||||
gp.set_data_ptr(data.data());
|
||||
gp.set_data_length(data.size());
|
||||
gp.set_streaming_width(4);
|
||||
sc_core::sc_time delay;
|
||||
intor->b_transport(gp, delay);
|
||||
wait(10_ns);
|
||||
|
||||
if ( gp.get_response_status() != tlm::TLM_OK_RESPONSE ) {
|
||||
// todo: improve output in case of exception, define own exception class to carry transaction-infos
|
||||
// ... i.e. out-of-range report with info about legal mem boundaries
|
||||
throw std::exception();
|
||||
}
|
||||
|
||||
// todo: use reinterpret_cast instead
|
||||
std::uint32_t rdat = data[3]<<24 | data[2]<<16 | data[1]<<8 | data[0];
|
||||
|
||||
LOG(logging::INFO) << "read_bus(0x" << std::hex << adr << ") -> " << rdat;
|
||||
return rdat;
|
||||
}
|
||||
|
||||
void test_initiator::reg_check(std::uint32_t adr, std::uint32_t exp)
|
||||
{
|
||||
uint32_t dat = read_bus(adr);
|
||||
if ( dat != exp ) {
|
||||
LOG(logging::ERROR) << "register check failed for address 0x" << std::hex << adr << ": " << dat << " != " << exp;
|
||||
} else {
|
||||
LOG(logging::INFO) << "register check passed for address 0x" << std::hex << adr << ": " << dat;
|
||||
}
|
||||
}
|
||||
|
||||
void test_initiator::core_irq_handler()
|
||||
{
|
||||
LOG(logging::INFO) << "core_interrupt_i edge detected -> " << core_interrupt_i.read();
|
||||
}
|
||||
|
||||
} /* namespace sysc */
|
||||
|
|
|
|||
|
|
@ -32,11 +32,21 @@ class test_initiator: public sc_core::sc_module {
|
|||
public:
|
||||
SC_HAS_PROCESS(test_initiator);
|
||||
tlm_utils::simple_initiator_socket<test_initiator, 32> intor;
|
||||
|
||||
sc_core::sc_in<bool> rst_i;
|
||||
sc_core::sc_vector<sc_core::sc_out<bool>> global_interrupts_o;
|
||||
sc_core::sc_in<bool> core_interrupt_i;
|
||||
sc_core::sc_in<bool> rst_i;
|
||||
test_initiator(sc_core::sc_module_name nm);
|
||||
protected:
|
||||
void run();
|
||||
void test_unique_irq();
|
||||
void test_frequent_irq();
|
||||
void test_parallel_irq();
|
||||
void test_irq_stress();
|
||||
void write_bus(std::uint32_t adr, std::uint32_t dat);
|
||||
std::uint32_t read_bus(std::uint32_t adr);
|
||||
void reg_check(std::uint32_t adr, std::uint32_t exp);
|
||||
|
||||
void core_irq_handler();
|
||||
};
|
||||
|
||||
} /* namespace sysc */
|
||||
|
|
|
|||
Loading…
Reference in New Issue