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adds pipelining of wr req to AXI/ACE pinlevel adapters

This commit is contained in:
Eyck Jentzsch 2024-05-08 17:20:26 +02:00
parent f8bd40cd60
commit c929dcb5ea
3 changed files with 26 additions and 3 deletions
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1
.gitignore vendored
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@ -41,6 +41,7 @@
/.venv/ /.venv/
/.pydevproject /.pydevproject
/*.fst /*.fst
/*.ftr
/*.gtkw /*.gtkw
/.envrc.* /.envrc.*
/.direnv/ /.direnv/

2
scc

@ -1 +1 @@
Subproject commit 40b696a98b0fe179f6e0413a4223418f84288e85 Subproject commit 2a1d3c1c2e8dae7c6b6fc7353d7ca8ae76357e06

26
tests/axi4_pin_level/narrow_burst_test.cpp
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@ -136,7 +136,7 @@ template <typename STATE> unsigned run_scenario(STATE& state) {
return cycles; return cycles;
} }
TEST_CASE("axi4_burst_alignment", "[AXI][pin-level]") { void axi4_burst_alignment(bool pipelined_wrreq, bool write_bp) {
struct { struct {
unsigned int ResetCycles{4}; unsigned int ResetCycles{4};
unsigned int BurstLengthByte{16}; unsigned int BurstLengthByte{16};
@ -148,6 +148,9 @@ TEST_CASE("axi4_burst_alignment", "[AXI][pin-level]") {
unsigned resp_cnt{0}; unsigned resp_cnt{0};
} state; } state;
auto& dut = factory::get<testbench>();
dut.intor_bfm.pipelined_wrreq = pipelined_wrreq;
dut.tgt_pe.wr_data_accept_delay.value = write_bp ? 1 : 0;
auto cycles = run_scenario(state); auto cycles = run_scenario(state);
REQUIRE(cycles < 1000); REQUIRE(cycles < 1000);
@ -175,7 +178,7 @@ TEST_CASE("axi4_burst_alignment", "[AXI][pin-level]") {
} }
} }
TEST_CASE("axi4_narrow_burst", "[AXI][pin-level]") { void axi4_narrow_burst(bool pipelined_wrreq, bool write_bp) {
struct { struct {
unsigned int ResetCycles{4}; unsigned int ResetCycles{4};
unsigned int BurstLengthByte{16}; unsigned int BurstLengthByte{16};
@ -187,6 +190,9 @@ TEST_CASE("axi4_narrow_burst", "[AXI][pin-level]") {
unsigned resp_cnt{0}; unsigned resp_cnt{0};
} state; } state;
auto& dut = factory::get<testbench>();
dut.intor_bfm.pipelined_wrreq = pipelined_wrreq;
dut.tgt_pe.wr_data_accept_delay.value = write_bp ? 1 : 0;
auto cycles = run_scenario(state); auto cycles = run_scenario(state);
REQUIRE(cycles < 1000); REQUIRE(cycles < 1000);
@ -209,3 +215,19 @@ TEST_CASE("axi4_narrow_burst", "[AXI][pin-level]") {
CHECK(is_equal(*send_tx[i], *recv_tx[i])); CHECK(is_equal(*send_tx[i], *recv_tx[i]));
} }
} }
TEST_CASE("axi4_burst_alignment", "[AXI][pin-level]") { axi4_burst_alignment(false, false); }
TEST_CASE("axi4_narrow_burst", "[AXI][pin-level]") { axi4_narrow_burst(false, false); }
TEST_CASE("axi4_burst_alignment_with_bp", "[AXI][pin-level]") { axi4_burst_alignment(false, true); }
TEST_CASE("axi4_narrow_burst_with_bp", "[AXI][pin-level]") { axi4_narrow_burst(false, true); }
TEST_CASE("axi4_burst_alignment_pipelined_write", "[AXI][pin-level]") { axi4_burst_alignment(true, false); }
TEST_CASE("axi4_narrow_burst_pipelined_write", "[AXI][pin-level]") { axi4_narrow_burst(true, false); }
TEST_CASE("axi4_burst_alignment_pipelined_write_with_bp", "[AXI][pin-level]") { axi4_burst_alignment(true, true); }
TEST_CASE("axi4_narrow_burst_pipelined_write_with_bp", "[AXI][pin-level]") { axi4_narrow_burst(true, true); }