From c929dcb5ea3d711e0cff4180ad11fc3f4ade3a9c Mon Sep 17 00:00:00 2001
From: Eyck Jentzsch <eyck@minres.com>
Date: Wed, 8 May 2024 17:20:26 +0200
Subject: [PATCH] adds pipelining of wr req to AXI/ACE pinlevel adapters

---
 .gitignore                                 |  1 +
 scc                                        |  2 +-
 tests/axi4_pin_level/narrow_burst_test.cpp | 26 ++++++++++++++++++++--
 3 files changed, 26 insertions(+), 3 deletions(-)

diff --git a/.gitignore b/.gitignore
index 9382033..af81461 100644
--- a/.gitignore
+++ b/.gitignore
@@ -41,6 +41,7 @@
 /.venv/
 /.pydevproject
 /*.fst
+/*.ftr
 /*.gtkw
 /.envrc.*
 /.direnv/
diff --git a/scc b/scc
index 40b696a..2a1d3c1 160000
--- a/scc
+++ b/scc
@@ -1 +1 @@
-Subproject commit 40b696a98b0fe179f6e0413a4223418f84288e85
+Subproject commit 2a1d3c1c2e8dae7c6b6fc7353d7ca8ae76357e06
diff --git a/tests/axi4_pin_level/narrow_burst_test.cpp b/tests/axi4_pin_level/narrow_burst_test.cpp
index 13eca15..3119369 100644
--- a/tests/axi4_pin_level/narrow_burst_test.cpp
+++ b/tests/axi4_pin_level/narrow_burst_test.cpp
@@ -136,7 +136,7 @@ template <typename STATE> unsigned run_scenario(STATE& state) {
     return cycles;
 }
 
-TEST_CASE("axi4_burst_alignment", "[AXI][pin-level]") {
+void axi4_burst_alignment(bool pipelined_wrreq, bool write_bp) {
     struct {
         unsigned int ResetCycles{4};
         unsigned int BurstLengthByte{16};
@@ -148,6 +148,9 @@ TEST_CASE("axi4_burst_alignment", "[AXI][pin-level]") {
         unsigned resp_cnt{0};
     } state;
 
+    auto& dut = factory::get<testbench>();
+    dut.intor_bfm.pipelined_wrreq = pipelined_wrreq;
+    dut.tgt_pe.wr_data_accept_delay.value = write_bp ? 1 : 0;
     auto cycles = run_scenario(state);
 
     REQUIRE(cycles < 1000);
@@ -175,7 +178,7 @@ TEST_CASE("axi4_burst_alignment", "[AXI][pin-level]") {
     }
 }
 
-TEST_CASE("axi4_narrow_burst", "[AXI][pin-level]") {
+void axi4_narrow_burst(bool pipelined_wrreq, bool write_bp) {
     struct {
         unsigned int ResetCycles{4};
         unsigned int BurstLengthByte{16};
@@ -187,6 +190,9 @@ TEST_CASE("axi4_narrow_burst", "[AXI][pin-level]") {
         unsigned resp_cnt{0};
     } state;
 
+    auto& dut = factory::get<testbench>();
+    dut.intor_bfm.pipelined_wrreq = pipelined_wrreq;
+    dut.tgt_pe.wr_data_accept_delay.value = write_bp ? 1 : 0;
     auto cycles = run_scenario(state);
 
     REQUIRE(cycles < 1000);
@@ -209,3 +215,19 @@ TEST_CASE("axi4_narrow_burst", "[AXI][pin-level]") {
             CHECK(is_equal(*send_tx[i], *recv_tx[i]));
     }
 }
+
+TEST_CASE("axi4_burst_alignment", "[AXI][pin-level]") { axi4_burst_alignment(false, false); }
+
+TEST_CASE("axi4_narrow_burst", "[AXI][pin-level]") { axi4_narrow_burst(false, false); }
+
+TEST_CASE("axi4_burst_alignment_with_bp", "[AXI][pin-level]") { axi4_burst_alignment(false, true); }
+
+TEST_CASE("axi4_narrow_burst_with_bp", "[AXI][pin-level]") { axi4_narrow_burst(false, true); }
+
+TEST_CASE("axi4_burst_alignment_pipelined_write", "[AXI][pin-level]") { axi4_burst_alignment(true, false); }
+
+TEST_CASE("axi4_narrow_burst_pipelined_write", "[AXI][pin-level]") { axi4_narrow_burst(true, false); }
+
+TEST_CASE("axi4_burst_alignment_pipelined_write_with_bp", "[AXI][pin-level]") { axi4_burst_alignment(true, true); }
+
+TEST_CASE("axi4_narrow_burst_pipelined_write_with_bp", "[AXI][pin-level]") { axi4_narrow_burst(true, true); }