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adds pipelining of wr req to AXI/ACE pinlevel adapters

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Eyck Jentzsch
2024-05-08 17:20:26 +02:00
parent f8bd40cd60
commit c929dcb5ea
3 changed files with 26 additions and 3 deletions
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.gitignore vendored
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@ -41,6 +41,7 @@
/.venv/
/.pydevproject
/*.fst
/*.ftr
/*.gtkw
/.envrc.*
/.direnv/