updates SCC
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#include <ahb/pin/initiator.h>
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#include <ahb/pin/target.h>
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#include <cci_configuration>
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#include <fstream>
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#include <scc/configurable_tracer.h>
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#include <scc/configurer.h>
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#include <scc/report.h>
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#include <scc/traceable.h>
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#include <scc/tracer.h>
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#include <tlm/scc/initiator_mixin.h>
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#include <tlm/scc/target_mixin.h>
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using namespace sc_core;
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using namespace scc;
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class testbench : public sc_module, public scc::traceable {
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public:
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enum { WIDTH = 64 };
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tlm::scc::initiator_mixin<tlm::tlm_initiator_socket<WIDTH>> isck{"isck"};
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ahb::pin::initiator<WIDTH> intor{"intor"};
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sc_core::sc_clock HCLK{"HCLK", 10_ns};
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sc_core::sc_signal<bool> HRESETn{"HRESETn"};
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sc_core::sc_signal<sc_dt::sc_uint<32>> HADDR{"HADDR"};
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sc_core::sc_signal<sc_dt::sc_uint<3>> HBURST{"HBURST"};
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sc_core::sc_signal<bool> HMASTLOCK{"HMASTLOCK"};
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sc_core::sc_signal<sc_dt::sc_uint<4>> HPROT{"HPROT"};
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sc_core::sc_signal<sc_dt::sc_uint<3>> HSIZE{"HSIZE"};
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sc_core::sc_signal<sc_dt::sc_uint<2>> HTRANS{"HTRANS"};
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sc_core::sc_signal<sc_dt::sc_uint<WIDTH>> HWDATA{"HWDATA"};
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sc_core::sc_signal<bool> HWRITE{"HWRITE"};
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sc_core::sc_signal<sc_dt::sc_uint<WIDTH>> HRDATA{"HRDATA"};
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sc_core::sc_signal<bool> HREADY{"HREADY"};
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sc_core::sc_signal<bool> HRESP{"HRESP"};
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sc_core::sc_signal<bool> HSEL{"HSEL"};
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ahb::pin::target<WIDTH> target{"target"};
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tlm::scc::target_mixin<tlm::tlm_target_socket<WIDTH>> tsck{"tsck"};
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testbench(sc_module_name nm)
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: sc_module(nm) {
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SC_HAS_PROCESS(testbench);
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isck(intor.tsckt);
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intor.HCLK_i(HCLK);
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intor.HRESETn_i(HRESETn);
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intor.HADDR_o(HADDR);
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intor.HBURST_o(HBURST);
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intor.HMASTLOCK_o(HMASTLOCK);
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intor.HPROT_o(HPROT);
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intor.HSIZE_o(HSIZE);
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intor.HTRANS_o(HTRANS);
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intor.HWDATA_o(HWDATA);
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intor.HWRITE_o(HWRITE);
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intor.HRDATA_i(HRDATA);
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intor.HREADY_i(HREADY);
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intor.HRESP_i(HRESP);
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target.HCLK_i(HCLK);
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target.HRESETn_i(HRESETn);
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target.HADDR_i(HADDR);
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target.HBURST_i(HBURST);
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target.HMASTLOCK_i(HMASTLOCK);
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target.HPROT_i(HPROT);
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target.HSIZE_i(HSIZE);
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target.HTRANS_i(HTRANS);
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target.HWDATA_i(HWDATA);
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target.HWRITE_i(HWRITE);
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target.HSEL_i(HSEL);
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target.HRDATA_o(HRDATA);
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target.HREADY_o(HREADY);
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target.HRESP_o(HRESP);
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target.isckt(tsck);
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SC_THREAD(run);
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tsck.register_b_transport([this](tlm::tlm_generic_payload& gp, sc_time& delay) {
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gp.set_response_status(tlm::TLM_OK_RESPONSE);
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if(gp.is_write()) {
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SCCINFO(SCMOD) << "Received write access to addr 0x" << std::hex << gp.get_address();
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} else {
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memset(gp.get_data_ptr(), 0x55, gp.get_data_length());
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SCCINFO(SCMOD) << "Received read access from addr 0x" << std::hex << gp.get_address();
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}
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});
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}
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void run() {
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HRESETn.write(false);
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for(size_t i = 0; i < 10; ++i)
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wait(HCLK.posedge_event());
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HRESETn.write(true);
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wait(HCLK.posedge_event());
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HSEL.write(true);
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tlm::tlm_generic_payload gp;
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uint8_t data[8];
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data[0] = 2;
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data[1] = 4;
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gp.set_address(0x1000);
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gp.set_data_length(8);
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gp.set_data_ptr(data);
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gp.set_streaming_width(8);
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gp.set_command(tlm::TLM_WRITE_COMMAND);
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sc_time delay;
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isck->b_transport(gp, delay);
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gp.set_address(0x1020);
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gp.set_data_length(8);
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gp.set_data_ptr(data);
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gp.set_streaming_width(8);
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gp.set_command(tlm::TLM_READ_COMMAND);
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delay = SC_ZERO_TIME;
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isck->b_transport(gp, delay);
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for(size_t i = 0; i < 10; ++i)
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wait(HCLK.posedge_event());
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sc_stop();
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}
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};
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int sc_main(int argc, char* argv[]) {
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sc_core::sc_report_handler::set_actions("/IEEE_Std_1666/deprecated", sc_core::SC_DO_NOTHING);
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sc_report_handler::set_actions(SC_ID_MORE_THAN_ONE_SIGNAL_DRIVER_, SC_DO_NOTHING);
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///////////////////////////////////////////////////////////////////////////
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// configure logging
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///////////////////////////////////////////////////////////////////////////
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scc::init_logging(scc::log::DEBUG);
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///////////////////////////////////////////////////////////////////////////
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// set up configuration and tracing
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///////////////////////////////////////////////////////////////////////////
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scc::configurer cfg("ahb_bfm.json");
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scc::configurable_tracer trace("ahb_bfm", tracer::TEXT, true, true);
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///////////////////////////////////////////////////////////////////////////
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// create modules/channels and trace
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///////////////////////////////////////////////////////////////////////////
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testbench tb("tb");
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trace.add_control();
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{
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std::ofstream of{"ahb_test.default.json"};
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if(of.is_open())
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cfg.dump_configuration(of);
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}
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cfg.configure();
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///////////////////////////////////////////////////////////////////////////
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// run the simulation
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///////////////////////////////////////////////////////////////////////////
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try {
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sc_core::sc_start(1_us);
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if(!sc_core::sc_end_of_simulation_invoked())
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sc_core::sc_stop();
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} catch(sc_core::sc_report& rep) {
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sc_core::sc_report_handler::get_handler()(rep, sc_core::SC_DISPLAY | sc_core::SC_STOP);
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}
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return 0;
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}
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2
scc
2
scc
@ -1 +1 @@
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Subproject commit 7e0777089bc86d60557ebe25d34d3f7244d97b53
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Subproject commit 440e1f6c45592e3464314df6a7174211f2c7112d
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