adds test for router default target DMI behavior
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scc
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scc
Submodule scc updated: 7a5fd95c58...50de0c564a
@@ -65,6 +65,7 @@ TEST_CASE("dmi_access", "[memory][tlm-level]") {
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do_dmi_access(dut.isck1, 16_MB - 1_MB, 16_MB);
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do_dmi_access(dut.isck1, 32_MB - 1_MB, 16_MB);
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do_dmi_access(dut.isck1, 48_MB - 1_MB, 4_MB);
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do_dmi_access(dut.isck0, 128_MB, 16_MB);
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sc_start(dut.clk.read());
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}
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@@ -28,12 +28,13 @@ struct testbench : public sc_core::sc_module {
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sc_core::sc_signal<bool> rst{"rst"};
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tlm::scc::initiator_mixin<tlm::tlm_initiator_socket<scc::LT>> isck0{"isck0"};
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tlm::scc::initiator_mixin<tlm::tlm_initiator_socket<scc::LT>> isck1{"isck1"};
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scc::router<scc::LT> router{"router", 5, 2};
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scc::router<scc::LT> router{"router", 6, 2};
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scc::memory_tl<1_kB, scc::LT> mem0{"mem0"};
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scc::memory_tl<1_kB, scc::LT> mem1{"mem1"};
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scc::memory_tl<18_MB, scc::LT> mem2{"mem2"};
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scc::memory_tl<24_MB, scc::LT> mem3{"mem3"};
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scc::memory_tl<88_MB, scc::LT> mem4{"mem4"};
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scc::memory<4_GB> mem5{"mem5"};
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testbench()
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: testbench(sc_core::sc_gen_unique_name("testbench", false)) {}
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@@ -48,6 +49,8 @@ struct testbench : public sc_core::sc_module {
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router.bind_target(mem2.target, 2, 16_MB, 16_MB);
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router.bind_target(mem3.target, 3, 32_MB, 20_MB);
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router.bind_target(mem4.target, 4, 64_MB, 20_MB, false);
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router.initiator[5].bind(mem5.target);
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router.set_default_target(5);
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mem0.clk_i(clk);
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mem1.clk_i(clk);
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mem2.clk_i(clk);
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