add ace_pin_level testcase and update scc
This commit is contained in:
parent
3f97fcc28c
commit
50bd12b4ec
2
scc
2
scc
@ -1 +1 @@
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Subproject commit 3d5f733ed40ffdbd8f9f788a5a5075fe0797498c
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Subproject commit a21316a97fff4953a3c08d32f6b97cf6d11d441e
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@ -1,6 +1,7 @@
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add_subdirectory(io-redirector)
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add_subdirectory(ordered_semaphore)
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add_subdirectory(axi4_pin_level)
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add_subdirectory(ace_pin_level)
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add_subdirectory(configuration)
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if(FULL_TEST_SUITE)
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add_subdirectory(sim_performance)
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9
tests/ace_pin_level/CMakeLists.txt
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9
tests/ace_pin_level/CMakeLists.txt
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project (ace_pin_level)
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add_executable(${PROJECT_NAME}
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ace_narrow_burst_test.cpp
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${test_util_SOURCE_DIR}/sc_main.cpp
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)
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target_link_libraries (${PROJECT_NAME} PUBLIC test_util)
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catch_discover_tests(${PROJECT_NAME})
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242
tests/ace_pin_level/ace_narrow_burst_test.cpp
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242
tests/ace_pin_level/ace_narrow_burst_test.cpp
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#include "testbench.h"
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#include <factory.h>
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#include <tlm/scc/tlm_gp_shared.h>
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#undef CHECK
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#include <catch2/catch_all.hpp>
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#include <unordered_map>
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using namespace sc_core;
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factory::add<testbench> tb;
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bool operator==(tlm::tlm_generic_payload const& a, tlm::tlm_generic_payload const& b){
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auto ret = true;
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ret &= a.get_command() == b.get_command();
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ret &= a.get_address() == b.get_address();
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ret &= a.get_data_length() == b.get_data_length();
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for(auto i=0u; i<a.get_data_length(); ++i)
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ret &= a.get_data_ptr()[i] == b.get_data_ptr()[i];
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// if(a.get_byte_enable_ptr() && b.get_byte_enable_ptr()) {
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// ret &= a.get_byte_enable_length() == b.get_byte_enable_length();
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// for(auto i=0u; i<a.get_byte_enable_length(); ++i)
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// ret &= a.get_byte_enable_ptr()[i] == b.get_byte_enable_ptr()[i];
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// }
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ret &= a.get_command() == b.get_command();
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//if(!ret) SCCWARN()<<"Comparison failed: "<<a<<" and "<<b;
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return ret;
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}
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template<typename bus_cfg>
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tlm::tlm_generic_payload* prepare_trans(uint64_t start_address, unsigned addr_incr, unsigned len, unsigned width, unsigned id) {
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auto trans = tlm::scc::tlm_mm<>::get().allocate<axi::axi4_extension>(len);
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trans->set_address(start_address);
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tlm::scc::setId(*trans, id);
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auto ext = trans->get_extension<axi::axi4_extension>();
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trans->set_data_length(len);
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trans->set_streaming_width(len);
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ext->set_size(scc::ilog2(width));
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sc_assert(len < (bus_cfg::BUSWIDTH / 8) || len % (bus_cfg::BUSWIDTH / 8) == 0);
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auto length = (len * 8 - 1) / (8*width);
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if(width==(bus_cfg::BUSWIDTH / 8) && start_address % (bus_cfg::BUSWIDTH / 8))
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length++;
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ext->set_length(length);
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// ext->set_burst(len * 8 > bus_cfg::buswidth ? axi::burst_e::INCR : axi::burst_e::FIXED);
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ext->set_burst(axi::burst_e::INCR);
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ext->set_id(id);
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return trans;
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}
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template<typename bus_cfg>
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tlm::tlm_generic_payload* prepare_trans_ace(uint64_t start_address, unsigned addr_incr, unsigned len, unsigned width, unsigned id) {
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auto trans = tlm::scc::tlm_mm<>::get().allocate<axi::ace_extension>(len);
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trans->set_address(start_address);
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tlm::scc::setId(*trans, id);
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auto ext = trans->get_extension<axi::ace_extension>();
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trans->set_data_length(len);
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trans->set_streaming_width(len);
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ext->set_size(scc::ilog2(width));
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sc_assert(len < (bus_cfg::BUSWIDTH / 8) || len % (bus_cfg::BUSWIDTH / 8) == 0);
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auto length = (len * 8 - 1) / (8*width);
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if(width==(bus_cfg::BUSWIDTH / 8) && start_address % (bus_cfg::BUSWIDTH / 8))
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length++;
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ext->set_length(length);
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// ext->set_burst(len * 8 > bus_cfg::buswidth ? axi::burst_e::INCR : axi::burst_e::FIXED);
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ext->set_burst(axi::burst_e::INCR);
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ext->set_id(id);
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ext->set_snoop(axi::snoop_e::READ_SHARED); // set it so that is_data_less return true???
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return trans;
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}
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inline void randomize(tlm::tlm_generic_payload& gp) {
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static uint8_t req_cnt{0};
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auto addr = gp.get_address();
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uint8_t const* src = reinterpret_cast<uint8_t const*>(&addr);
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for(size_t i = 0; i < gp.get_data_length(); ++i) {
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*(gp.get_data_ptr() + i) = i % 2 ? i : req_cnt;
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}
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req_cnt++;
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}
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template<typename STATE>
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unsigned run_scenario(STATE& state){
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auto& dut = factory::get<testbench>();
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dut.axi_tgt_pe.set_operation_cb([&state](axi::axi_protocol_types::tlm_payload_type& trans) -> unsigned {
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auto id = axi::get_axi_id(trans);
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if(trans.is_read()) {
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for(size_t i = 0; i < trans.get_data_length(); ++i) {
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*(trans.get_data_ptr() + i) = i % 2 ? 123 : (state.resp_cnt+128);
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}
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state.read_tx[id].second.emplace_back(&trans);
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}
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if(trans.is_write())
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state.write_tx[id].second.emplace_back(&trans);
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SCCDEBUG(__FUNCTION__)<<"RX: "<<trans;
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state.resp_cnt++;
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return 0;
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});
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dut.rst.write(false);
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sc_start(state.ResetCycles*dut.clk.period());
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dut.rst.write(true);
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sc_start(dut.clk.period());
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auto run1 = sc_spawn([&dut, &state](){
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unsigned int StartAddr{0x0};
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for(int i = 0; i < state.NumberOfIterations; ++i) {
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// tlm::scc::tlm_gp_shared_ptr trans = prepare_trans<testbench::bus_cfg>(StartAddr, 4, state.BurstLengthByte, state.BurstSizeBytes, 1);
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tlm::scc::tlm_gp_shared_ptr trans = prepare_trans_ace<testbench::bus_cfg>(StartAddr, 4, state.BurstLengthByte, state.BurstSizeBytes, 1);
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trans->set_command(tlm::TLM_READ_COMMAND);
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SCCDEBUG(__FUNCTION__) << "run1, iteration " << i <<" TX: "<<*trans;
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dut.intor_pe.transport(*trans, false);
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state.read_tx[axi::get_axi_id(*trans)].first.emplace_back(trans);
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StartAddr += state.BurstSizeBytes;
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}
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});
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/*
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auto run2 = sc_spawn([&dut, &state](){
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unsigned int StartAddr{0x2000};
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for(int i = 0; i < state.NumberOfIterations; ++i) {
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tlm::scc::tlm_gp_shared_ptr trans = prepare_trans_ace<testbench::bus_cfg>(StartAddr, 4, state.BurstLengthByte, state.BurstSizeBytes, 2);
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trans->set_command(tlm::TLM_WRITE_COMMAND);
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randomize(*trans);
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SCCDEBUG(__FUNCTION__) << "run2, iteration " << i <<" TX: "<<*trans;
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dut.intor_pe.transport(*trans, false);
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state.write_tx[axi::get_axi_id(*trans)].first.emplace_back(trans);
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StartAddr += state.BurstSizeBytes;
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}
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});
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auto run3 = sc_spawn([&dut, &state](){
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unsigned int StartAddr{0x1000};
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for(int i = 0; i < state.NumberOfIterations; ++i) {
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tlm::scc::tlm_gp_shared_ptr trans = prepare_trans_ace<testbench::bus_cfg>(StartAddr, 4, state.BurstLengthByte, state.BurstSizeBytes, 3);
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trans->set_command(tlm::TLM_READ_COMMAND);
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SCCDEBUG(__FUNCTION__) << "run3, iteration " << i <<" TX: "<<*trans;
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dut.intor_pe.transport(*trans, false);
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state.read_tx[axi::get_axi_id(*trans)].first.emplace_back(trans);
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StartAddr += state.BurstSizeBytes;
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}
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});
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auto run4 = sc_spawn([&dut, &state](){
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unsigned int StartAddr{0x3000};
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for(int i = 0; i < state.NumberOfIterations; ++i) {
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tlm::scc::tlm_gp_shared_ptr trans = prepare_trans_ace<testbench::bus_cfg>(StartAddr, 4, state.BurstLengthByte, state.BurstSizeBytes, 4);
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trans->set_command(tlm::TLM_WRITE_COMMAND);
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randomize(*trans);
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SCCDEBUG(__FUNCTION__) << "run4, iteration " << i <<" TX: "<<*trans;
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dut.intor_pe.transport(*trans, false);
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state.write_tx[axi::get_axi_id(*trans)].first.emplace_back(trans);
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StartAddr += state.BurstSizeBytes;
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}
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});
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*/
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unsigned cycles{0};
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// while(cycles<1000 && !(run1.terminated() && run2.terminated() && run3.terminated() && run4.terminated())){
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while(cycles<1000 && !(run1.terminated())){
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sc_start(10 * dut.clk.period());
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cycles+=10;
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}
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return cycles;
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}
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TEST_CASE("ace_burst_alignment", "[AXI][pin-level]") {
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struct {
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unsigned int ResetCycles{4};
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// unsigned int BurstLengthByte{16};
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unsigned int BurstLengthByte{32};
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unsigned int BurstSizeBytes{8};
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// unsigned int NumberOfIterations{8};
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unsigned int NumberOfIterations{1};
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std::unordered_map<unsigned, std::pair<std::vector<tlm::scc::tlm_gp_shared_ptr>, std::vector<tlm::scc::tlm_gp_shared_ptr>>> read_tx;
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std::unordered_map<unsigned, std::pair<std::vector<tlm::scc::tlm_gp_shared_ptr>, std::vector<tlm::scc::tlm_gp_shared_ptr>>> write_tx;
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unsigned resp_cnt{0};
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} state;
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auto cycles = run_scenario(state);
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REQUIRE(cycles<1000);
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REQUIRE(sc_report_handler::get_count(SC_ERROR) == 0);
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REQUIRE(sc_report_handler::get_count(SC_WARNING) == 0);
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REQUIRE(state.resp_cnt==4*state.NumberOfIterations);
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for(auto& e: state.write_tx) {
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auto const& send_tx = e.second.first;
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auto const& recv_tx = e.second.second;
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REQUIRE(send_tx.size() == recv_tx.size());
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for(auto i = 0; i<send_tx.size(); ++i) {
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REQUIRE(send_tx[i]->get_response_status() == tlm::TLM_OK_RESPONSE);
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CHECK(*send_tx[i] == *recv_tx[i]);
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}
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}
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for(auto& e: state.read_tx) {
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auto const& send_tx = e.second.first;
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auto const& recv_tx = e.second.second;
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REQUIRE(send_tx.size() == recv_tx.size());
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for(auto i = 0; i<send_tx.size(); ++i){
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REQUIRE(send_tx[i]->get_response_status() == tlm::TLM_OK_RESPONSE);
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CHECK(*send_tx[i] == *recv_tx[i]);
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}
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}
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}
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TEST_CASE("axi4_narrow_burst", "[AXI][pin-level]") {
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struct {
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unsigned int ResetCycles{4};
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unsigned int BurstLengthByte{32};
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// unsigned int BurstLengthByte{16};
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unsigned int BurstSizeBytes{4};
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// unsigned int NumberOfIterations{8};
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unsigned int NumberOfIterations{1};
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std::unordered_map<unsigned, std::pair<std::vector<tlm::scc::tlm_gp_shared_ptr>, std::vector<tlm::scc::tlm_gp_shared_ptr>>> read_tx;
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std::unordered_map<unsigned, std::pair<std::vector<tlm::scc::tlm_gp_shared_ptr>, std::vector<tlm::scc::tlm_gp_shared_ptr>>> write_tx;
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unsigned resp_cnt{0};
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} state;
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auto cycles = run_scenario(state);
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REQUIRE(cycles<1000);
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REQUIRE(sc_report_handler::get_count(SC_ERROR) == 0);
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REQUIRE(sc_report_handler::get_count(SC_WARNING) == 0);
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REQUIRE(state.resp_cnt==4*state.NumberOfIterations);
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for(auto& e: state.write_tx) {
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auto const& send_tx = e.second.first;
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auto const& recv_tx = e.second.second;
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REQUIRE(send_tx.size() == recv_tx.size());
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for(auto i = 0; i<send_tx.size(); ++i)
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CHECK(*send_tx[i] == *recv_tx[i]);
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}
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for(auto& e: state.read_tx) {
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auto const& send_tx = e.second.first;
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auto const& recv_tx = e.second.second;
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REQUIRE(send_tx.size() == recv_tx.size());
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for(auto i = 0; i<send_tx.size(); ++i)
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CHECK(*send_tx[i] == *recv_tx[i]);
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}
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}
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83
tests/ace_pin_level/testbench.h
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83
tests/ace_pin_level/testbench.h
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#ifndef _TESTBENCH_H_
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#define _TESTBENCH_H_
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#include <axi/pe/axi_initiator.h>
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#include <axi/pe/simple_target.h>
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#include <axi/pe/simple_ace_target.h>
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#include <axi/pin/ace_initiator.h>
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#include <axi/pin/ace_target.h>
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#include <axi/scv/recorder_modules.h>
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#include <scc.h>
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using namespace sc_core;
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using namespace axi;
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using namespace axi::pe;
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class testbench : public sc_core::sc_module {
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public:
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using bus_cfg = axi::ace_cfg</*BUSWIDTH=*/64, /*ADDRWIDTH=*/32, /*IDWIDTH=*/4, /*USERWIDTH=*/1>;
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sc_core::sc_time clk_period{10, sc_core::SC_NS};
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sc_core::sc_clock clk{"clk", clk_period, 0.5, sc_core::SC_ZERO_TIME, true};
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sc_core::sc_signal<bool> rst{"rst"};
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// initiator side
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axi::ace_initiator_socket<bus_cfg::BUSWIDTH> intor{"ace_intor"};
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axi::pin::ace_initiator<bus_cfg> intor_bfm{"ace_intor_bfm"};
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// signal accurate bus
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axi::aw_ch_ace<bus_cfg, axi::signal_types> aw;
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axi::wdata_ch_ace<bus_cfg, axi::signal_types> wdata;
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axi::b_ch_ace<bus_cfg, axi::signal_types> b;
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axi::ar_ch_ace<bus_cfg, axi::signal_types> ar;
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axi::rresp_ch_ace<bus_cfg, axi::signal_types> rresp;
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axi::pin::ace_target<bus_cfg> tgt_bfm{"ace_tgt_bfm"};
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// target side
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axi::ace_target_socket<bus_cfg::BUSWIDTH> tgt_ace{"tgt_ace"};
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axi::axi_target_socket<bus_cfg::BUSWIDTH> tgt_axi{"tgt_axi"};
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// engines
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axi::pe::ace_initiator<bus_cfg::BUSWIDTH> intor_pe;
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axi::pe::simple_target<bus_cfg::BUSWIDTH> axi_tgt_pe;
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axi::pe::simple_ace_target<bus_cfg::BUSWIDTH> ace_tgt_pe;
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public:
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SC_HAS_PROCESS(testbench);
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testbench(): testbench("testbench") {}
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testbench(sc_core::sc_module_name nm)
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: sc_core::sc_module(nm)
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, intor_pe("ace_intor_pe", intor)
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, ace_tgt_pe("ace_tgt_pe", tgt_ace)
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, axi_tgt_pe("axi_tgt_pe", tgt_axi) {
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intor_pe.clk_i(clk);
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intor_bfm.clk_i(clk);
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tgt_bfm.clk_i(clk);
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axi_tgt_pe.clk_i(clk);
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ace_tgt_pe.clk_i(clk);
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// pe socket to recorder
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intor(intor_bfm.tsckt);
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// bfm to signals
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intor_bfm.bind_aw(aw);
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intor_bfm.bind_w(wdata);
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intor_bfm.bind_b(b);
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intor_bfm.bind_ar(ar);
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intor_bfm.bind_r(rresp);
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// signals to bfm
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tgt_bfm.bind_aw(aw);
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tgt_bfm.bind_w(wdata);
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tgt_bfm.bind_b(b);
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tgt_bfm.bind_ar(ar);
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tgt_bfm.bind_r(rresp);
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// bfm to recorder
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tgt_bfm.isckt(tgt_ace);
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ace_tgt_pe.isckt_axi(tgt_axi);
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}
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void run1() {
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}
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};
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#endif // _TESTBENCH_H_
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