diff --git a/scc b/scc index 3d5f733..a21316a 160000 --- a/scc +++ b/scc @@ -1 +1 @@ -Subproject commit 3d5f733ed40ffdbd8f9f788a5a5075fe0797498c +Subproject commit a21316a97fff4953a3c08d32f6b97cf6d11d441e diff --git a/tests/CMakeLists.txt b/tests/CMakeLists.txt index 173dc7f..f50c669 100644 --- a/tests/CMakeLists.txt +++ b/tests/CMakeLists.txt @@ -1,6 +1,7 @@ add_subdirectory(io-redirector) add_subdirectory(ordered_semaphore) add_subdirectory(axi4_pin_level) +add_subdirectory(ace_pin_level) add_subdirectory(configuration) if(FULL_TEST_SUITE) add_subdirectory(sim_performance) diff --git a/tests/ace_pin_level/CMakeLists.txt b/tests/ace_pin_level/CMakeLists.txt new file mode 100644 index 0000000..78d5cf1 --- /dev/null +++ b/tests/ace_pin_level/CMakeLists.txt @@ -0,0 +1,9 @@ +project (ace_pin_level) + +add_executable(${PROJECT_NAME} + ace_narrow_burst_test.cpp + ${test_util_SOURCE_DIR}/sc_main.cpp +) +target_link_libraries (${PROJECT_NAME} PUBLIC test_util) + +catch_discover_tests(${PROJECT_NAME}) diff --git a/tests/ace_pin_level/ace_narrow_burst_test.cpp b/tests/ace_pin_level/ace_narrow_burst_test.cpp new file mode 100644 index 0000000..5800a76 --- /dev/null +++ b/tests/ace_pin_level/ace_narrow_burst_test.cpp @@ -0,0 +1,242 @@ + +#include "testbench.h" +#include +#include +#undef CHECK +#include +#include + +using namespace sc_core; + +factory::add tb; + +bool operator==(tlm::tlm_generic_payload const& a, tlm::tlm_generic_payload const& b){ + auto ret = true; + ret &= a.get_command() == b.get_command(); + ret &= a.get_address() == b.get_address(); + ret &= a.get_data_length() == b.get_data_length(); + for(auto i=0u; i +tlm::tlm_generic_payload* prepare_trans(uint64_t start_address, unsigned addr_incr, unsigned len, unsigned width, unsigned id) { + auto trans = tlm::scc::tlm_mm<>::get().allocate(len); + trans->set_address(start_address); + tlm::scc::setId(*trans, id); + auto ext = trans->get_extension(); + trans->set_data_length(len); + trans->set_streaming_width(len); + ext->set_size(scc::ilog2(width)); + sc_assert(len < (bus_cfg::BUSWIDTH / 8) || len % (bus_cfg::BUSWIDTH / 8) == 0); + auto length = (len * 8 - 1) / (8*width); + if(width==(bus_cfg::BUSWIDTH / 8) && start_address % (bus_cfg::BUSWIDTH / 8)) + length++; + ext->set_length(length); + // ext->set_burst(len * 8 > bus_cfg::buswidth ? axi::burst_e::INCR : axi::burst_e::FIXED); + ext->set_burst(axi::burst_e::INCR); + ext->set_id(id); + return trans; +} + +template +tlm::tlm_generic_payload* prepare_trans_ace(uint64_t start_address, unsigned addr_incr, unsigned len, unsigned width, unsigned id) { + auto trans = tlm::scc::tlm_mm<>::get().allocate(len); + trans->set_address(start_address); + tlm::scc::setId(*trans, id); + auto ext = trans->get_extension(); + trans->set_data_length(len); + trans->set_streaming_width(len); + ext->set_size(scc::ilog2(width)); + sc_assert(len < (bus_cfg::BUSWIDTH / 8) || len % (bus_cfg::BUSWIDTH / 8) == 0); + auto length = (len * 8 - 1) / (8*width); + if(width==(bus_cfg::BUSWIDTH / 8) && start_address % (bus_cfg::BUSWIDTH / 8)) + length++; + ext->set_length(length); + // ext->set_burst(len * 8 > bus_cfg::buswidth ? axi::burst_e::INCR : axi::burst_e::FIXED); + ext->set_burst(axi::burst_e::INCR); + ext->set_id(id); + ext->set_snoop(axi::snoop_e::READ_SHARED); // set it so that is_data_less return true??? + return trans; +} + +inline void randomize(tlm::tlm_generic_payload& gp) { + static uint8_t req_cnt{0}; + auto addr = gp.get_address(); + uint8_t const* src = reinterpret_cast(&addr); + for(size_t i = 0; i < gp.get_data_length(); ++i) { + *(gp.get_data_ptr() + i) = i % 2 ? i : req_cnt; + } + req_cnt++; +} + +template +unsigned run_scenario(STATE& state){ + auto& dut = factory::get(); + + dut.axi_tgt_pe.set_operation_cb([&state](axi::axi_protocol_types::tlm_payload_type& trans) -> unsigned { + auto id = axi::get_axi_id(trans); + if(trans.is_read()) { + for(size_t i = 0; i < trans.get_data_length(); ++i) { + *(trans.get_data_ptr() + i) = i % 2 ? 123 : (state.resp_cnt+128); + } + state.read_tx[id].second.emplace_back(&trans); + } + if(trans.is_write()) + state.write_tx[id].second.emplace_back(&trans); + SCCDEBUG(__FUNCTION__)<<"RX: "<(StartAddr, 4, state.BurstLengthByte, state.BurstSizeBytes, 1); + tlm::scc::tlm_gp_shared_ptr trans = prepare_trans_ace(StartAddr, 4, state.BurstLengthByte, state.BurstSizeBytes, 1); + trans->set_command(tlm::TLM_READ_COMMAND); + SCCDEBUG(__FUNCTION__) << "run1, iteration " << i <<" TX: "<<*trans; + dut.intor_pe.transport(*trans, false); + state.read_tx[axi::get_axi_id(*trans)].first.emplace_back(trans); + StartAddr += state.BurstSizeBytes; + } + }); +/* + auto run2 = sc_spawn([&dut, &state](){ + unsigned int StartAddr{0x2000}; + for(int i = 0; i < state.NumberOfIterations; ++i) { + tlm::scc::tlm_gp_shared_ptr trans = prepare_trans_ace(StartAddr, 4, state.BurstLengthByte, state.BurstSizeBytes, 2); + trans->set_command(tlm::TLM_WRITE_COMMAND); + randomize(*trans); + SCCDEBUG(__FUNCTION__) << "run2, iteration " << i <<" TX: "<<*trans; + dut.intor_pe.transport(*trans, false); + state.write_tx[axi::get_axi_id(*trans)].first.emplace_back(trans); + StartAddr += state.BurstSizeBytes; + } + }); + auto run3 = sc_spawn([&dut, &state](){ + unsigned int StartAddr{0x1000}; + for(int i = 0; i < state.NumberOfIterations; ++i) { + tlm::scc::tlm_gp_shared_ptr trans = prepare_trans_ace(StartAddr, 4, state.BurstLengthByte, state.BurstSizeBytes, 3); + trans->set_command(tlm::TLM_READ_COMMAND); + SCCDEBUG(__FUNCTION__) << "run3, iteration " << i <<" TX: "<<*trans; + dut.intor_pe.transport(*trans, false); + state.read_tx[axi::get_axi_id(*trans)].first.emplace_back(trans); + StartAddr += state.BurstSizeBytes; + } + }); + auto run4 = sc_spawn([&dut, &state](){ + unsigned int StartAddr{0x3000}; + for(int i = 0; i < state.NumberOfIterations; ++i) { + tlm::scc::tlm_gp_shared_ptr trans = prepare_trans_ace(StartAddr, 4, state.BurstLengthByte, state.BurstSizeBytes, 4); + trans->set_command(tlm::TLM_WRITE_COMMAND); + randomize(*trans); + SCCDEBUG(__FUNCTION__) << "run4, iteration " << i <<" TX: "<<*trans; + dut.intor_pe.transport(*trans, false); + state.write_tx[axi::get_axi_id(*trans)].first.emplace_back(trans); + StartAddr += state.BurstSizeBytes; + } + }); +*/ + unsigned cycles{0}; + // while(cycles<1000 && !(run1.terminated() && run2.terminated() && run3.terminated() && run4.terminated())){ + while(cycles<1000 && !(run1.terminated())){ + sc_start(10 * dut.clk.period()); + cycles+=10; + } + return cycles; +} + +TEST_CASE("ace_burst_alignment", "[AXI][pin-level]") { + struct { + unsigned int ResetCycles{4}; + // unsigned int BurstLengthByte{16}; + unsigned int BurstLengthByte{32}; + unsigned int BurstSizeBytes{8}; +// unsigned int NumberOfIterations{8}; + unsigned int NumberOfIterations{1}; + std::unordered_map, std::vector>> read_tx; + std::unordered_map, std::vector>> write_tx; + unsigned resp_cnt{0}; + } state; + + auto cycles = run_scenario(state); + + REQUIRE(cycles<1000); + REQUIRE(sc_report_handler::get_count(SC_ERROR) == 0); + REQUIRE(sc_report_handler::get_count(SC_WARNING) == 0); + + REQUIRE(state.resp_cnt==4*state.NumberOfIterations); + for(auto& e: state.write_tx) { + auto const& send_tx = e.second.first; + auto const& recv_tx = e.second.second; + REQUIRE(send_tx.size() == recv_tx.size()); + for(auto i = 0; iget_response_status() == tlm::TLM_OK_RESPONSE); + CHECK(*send_tx[i] == *recv_tx[i]); + } + + } + for(auto& e: state.read_tx) { + auto const& send_tx = e.second.first; + auto const& recv_tx = e.second.second; + REQUIRE(send_tx.size() == recv_tx.size()); + for(auto i = 0; iget_response_status() == tlm::TLM_OK_RESPONSE); + CHECK(*send_tx[i] == *recv_tx[i]); + } + } +} + +TEST_CASE("axi4_narrow_burst", "[AXI][pin-level]") { + struct { + unsigned int ResetCycles{4}; + unsigned int BurstLengthByte{32}; + // unsigned int BurstLengthByte{16}; + unsigned int BurstSizeBytes{4}; + // unsigned int NumberOfIterations{8}; + unsigned int NumberOfIterations{1}; + std::unordered_map, std::vector>> read_tx; + std::unordered_map, std::vector>> write_tx; + unsigned resp_cnt{0}; + } state; + + auto cycles = run_scenario(state); + + REQUIRE(cycles<1000); + REQUIRE(sc_report_handler::get_count(SC_ERROR) == 0); + REQUIRE(sc_report_handler::get_count(SC_WARNING) == 0); + + REQUIRE(state.resp_cnt==4*state.NumberOfIterations); + for(auto& e: state.write_tx) { + auto const& send_tx = e.second.first; + auto const& recv_tx = e.second.second; + REQUIRE(send_tx.size() == recv_tx.size()); + for(auto i = 0; i +#include +#include +#include +#include +#include +#include + +using namespace sc_core; +using namespace axi; +using namespace axi::pe; + +class testbench : public sc_core::sc_module { +public: + using bus_cfg = axi::ace_cfg; + + sc_core::sc_time clk_period{10, sc_core::SC_NS}; + sc_core::sc_clock clk{"clk", clk_period, 0.5, sc_core::SC_ZERO_TIME, true}; + sc_core::sc_signal rst{"rst"}; + // initiator side + axi::ace_initiator_socket intor{"ace_intor"}; + + axi::pin::ace_initiator intor_bfm{"ace_intor_bfm"}; + // signal accurate bus + axi::aw_ch_ace aw; + axi::wdata_ch_ace wdata; + axi::b_ch_ace b; + axi::ar_ch_ace ar; + axi::rresp_ch_ace rresp; + + axi::pin::ace_target tgt_bfm{"ace_tgt_bfm"}; + // target side + axi::ace_target_socket tgt_ace{"tgt_ace"}; + axi::axi_target_socket tgt_axi{"tgt_axi"}; + // engines + axi::pe::ace_initiator intor_pe; + axi::pe::simple_target axi_tgt_pe; + axi::pe::simple_ace_target ace_tgt_pe; + +public: + SC_HAS_PROCESS(testbench); + testbench(): testbench("testbench") {} + testbench(sc_core::sc_module_name nm) + : sc_core::sc_module(nm) + , intor_pe("ace_intor_pe", intor) + , ace_tgt_pe("ace_tgt_pe", tgt_ace) + , axi_tgt_pe("axi_tgt_pe", tgt_axi) { + intor_pe.clk_i(clk); + intor_bfm.clk_i(clk); + tgt_bfm.clk_i(clk); + axi_tgt_pe.clk_i(clk); + ace_tgt_pe.clk_i(clk); + // pe socket to recorder + intor(intor_bfm.tsckt); + + // bfm to signals + intor_bfm.bind_aw(aw); + intor_bfm.bind_w(wdata); + intor_bfm.bind_b(b); + intor_bfm.bind_ar(ar); + intor_bfm.bind_r(rresp); + // signals to bfm + tgt_bfm.bind_aw(aw); + tgt_bfm.bind_w(wdata); + tgt_bfm.bind_b(b); + tgt_bfm.bind_ar(ar); + tgt_bfm.bind_r(rresp); + // bfm to recorder + tgt_bfm.isckt(tgt_ace); + + ace_tgt_pe.isckt_axi(tgt_axi); + + } + + + void run1() { + } +}; + +#endif // _TESTBENCH_H_