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simplifies AXI4 tests

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This commit is contained in:
Eyck Jentzsch 2022-10-03 11:26:29 +02:00
parent e0c3e3d898
commit 0345537c62
1 changed files with 53 additions and 60 deletions
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113
tests/axi4_pin_level/narrow_burst_test.cpp
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@ -29,8 +29,7 @@ bool operator==(tlm::tlm_generic_payload const& a, tlm::tlm_generic_payload cons
}
template<typename bus_cfg>
tlm::tlm_generic_payload* prepare_trans(uint64_t start_address, unsigned addr_incr, unsigned len, unsigned width, unsigned id_offs) {
static uint8_t id{0};
tlm::tlm_generic_payload* prepare_trans(uint64_t start_address, unsigned addr_incr, unsigned len, unsigned width, unsigned id) {
auto trans = tlm::scc::tlm_mm<>::get().allocate<axi::axi4_extension>(len);
trans->set_address(start_address);
tlm::scc::setId(*trans, id);
@ -46,7 +45,6 @@ tlm::tlm_generic_payload* prepare_trans(uint64_t start_address, unsigned addr_in
// ext->set_burst(len * 8 > bus_cfg::buswidth ? axi::burst_e::INCR : axi::burst_e::FIXED);
ext->set_burst(axi::burst_e::INCR);
ext->set_id(id);
id = (id + 1) % 8;
return trans;
}
@ -61,7 +59,7 @@ inline void randomize(tlm::tlm_generic_payload& gp) {
}
template<typename STATE>
void run_scenario(STATE& state){
unsigned run_scenario(STATE& state){
auto& dut = factory::get<testbench>();
dut.tgt_pe.set_operation_cb([&state](axi::axi_protocol_types::tlm_payload_type& trans) -> unsigned {
auto id = axi::get_axi_id(trans);
@ -86,66 +84,56 @@ void run_scenario(STATE& state){
auto run1 = sc_spawn([&dut, &state](){
unsigned int StartAddr{0x0};
for(int i = 0; i < state.NumberOfIterations; ++i) {
SCCDEBUG(__FUNCTION__) << "run0 executing transactions in iteration " << i;
{ // 1
tlm::scc::tlm_gp_shared_ptr trans = prepare_trans<testbench::bus_cfg>(StartAddr, 4, state.BurstLengthByte, state.BurstSizeBytes, 0);
randomize(*trans);
trans->set_command(tlm::TLM_READ_COMMAND);
SCCDEBUG(__FUNCTION__)<<"TX: "<<*trans;
dut.intor_pe.transport(*trans, false);
auto id = axi::get_axi_id(*trans);
state.read_tx[id].first.emplace_back(trans);
if(trans->get_response_status() != tlm::TLM_OK_RESPONSE)
SCCERR(__FUNCTION__) << "Invalid response status" << trans->get_response_string();
}
{ // 2
tlm::scc::tlm_gp_shared_ptr trans = prepare_trans<testbench::bus_cfg>(StartAddr, 4, state.BurstLengthByte, state.BurstSizeBytes, 0);
trans->set_command(tlm::TLM_WRITE_COMMAND);
randomize(*trans);
SCCDEBUG(__FUNCTION__)<<"TX: "<<*trans;
dut.intor_pe.transport(*trans, false);
auto id = axi::get_axi_id(*trans);
state.write_tx[id].first.emplace_back(trans);
if(trans->get_response_status() != tlm::TLM_OK_RESPONSE)
SCCERR(__FUNCTION__) << "Invalid response status" << trans->get_response_string();
}
tlm::scc::tlm_gp_shared_ptr trans = prepare_trans<testbench::bus_cfg>(StartAddr, 4, state.BurstLengthByte, state.BurstSizeBytes, 1);
trans->set_command(tlm::TLM_READ_COMMAND);
SCCDEBUG(__FUNCTION__) << "run1, iteration " << i <<" TX: "<<*trans;
dut.intor_pe.transport(*trans, false);
state.read_tx[axi::get_axi_id(*trans)].first.emplace_back(trans);
StartAddr += state.BurstSizeBytes;
}
});
auto run2 = sc_spawn([&dut, &state](){
wait(0_ns);
unsigned int StartAddr{0x1000};
unsigned int StartAddr{0x2000};
for(int i = 0; i < state.NumberOfIterations; ++i) {
SCCDEBUG(__FUNCTION__) << "run1 executing transactions in iteration " << i;
{ // 1
tlm::scc::tlm_gp_shared_ptr trans = prepare_trans<testbench::bus_cfg>(StartAddr, 4, state.BurstLengthByte, state.BurstSizeBytes, 0x8);
randomize(*trans);
trans->set_command(tlm::TLM_READ_COMMAND);
SCCDEBUG(__FUNCTION__)<<"TX: "<<*trans;
dut.intor_pe.transport(*trans, false);
auto id = axi::get_axi_id(*trans);
state.read_tx[id].first.emplace_back(trans);
if(trans->get_response_status() != tlm::TLM_OK_RESPONSE)
SCCERR(__FUNCTION__) << "Invalid response status" << trans->get_response_string();
}
{ // 2
tlm::scc::tlm_gp_shared_ptr trans = prepare_trans<testbench::bus_cfg>(StartAddr, 4, state.BurstLengthByte, state.BurstSizeBytes, 0x8);
trans->set_command(tlm::TLM_WRITE_COMMAND);
randomize(*trans);
SCCDEBUG(__FUNCTION__)<<"TX: "<<*trans;
dut.intor_pe.transport(*trans, false);
auto id = axi::get_axi_id(*trans);
state.write_tx[id].first.emplace_back(trans);
if(trans->get_response_status() != tlm::TLM_OK_RESPONSE)
SCCERR(__FUNCTION__) << "Invalid response status" << trans->get_response_string();
}
tlm::scc::tlm_gp_shared_ptr trans = prepare_trans<testbench::bus_cfg>(StartAddr, 4, state.BurstLengthByte, state.BurstSizeBytes, 2);
trans->set_command(tlm::TLM_WRITE_COMMAND);
randomize(*trans);
SCCDEBUG(__FUNCTION__) << "run2, iteration " << i <<" TX: "<<*trans;
dut.intor_pe.transport(*trans, false);
state.write_tx[axi::get_axi_id(*trans)].first.emplace_back(trans);
StartAddr += state.BurstSizeBytes;
}
});
auto run3 = sc_spawn([&dut, &state](){
unsigned int StartAddr{0x1000};
for(int i = 0; i < state.NumberOfIterations; ++i) {
tlm::scc::tlm_gp_shared_ptr trans = prepare_trans<testbench::bus_cfg>(StartAddr, 4, state.BurstLengthByte, state.BurstSizeBytes, 3);
trans->set_command(tlm::TLM_READ_COMMAND);
SCCDEBUG(__FUNCTION__) << "run3, iteration " << i <<" TX: "<<*trans;
dut.intor_pe.transport(*trans, false);
state.read_tx[axi::get_axi_id(*trans)].first.emplace_back(trans);
StartAddr += state.BurstSizeBytes;
}
});
auto run4 = sc_spawn([&dut, &state](){
unsigned int StartAddr{0x3000};
for(int i = 0; i < state.NumberOfIterations; ++i) {
tlm::scc::tlm_gp_shared_ptr trans = prepare_trans<testbench::bus_cfg>(StartAddr, 4, state.BurstLengthByte, state.BurstSizeBytes, 4);
trans->set_command(tlm::TLM_WRITE_COMMAND);
randomize(*trans);
SCCDEBUG(__FUNCTION__) << "run4, iteration " << i <<" TX: "<<*trans;
dut.intor_pe.transport(*trans, false);
state.write_tx[axi::get_axi_id(*trans)].first.emplace_back(trans);
StartAddr += state.BurstSizeBytes;
}
});
sc_start(120 * dut.clk.period());
REQUIRE(run1.terminated());
REQUIRE(run2.terminated());
unsigned cycles{0};
while(cycles<1000 && !(run1.terminated() && run2.terminated() && run3.terminated() && run4.terminated())){
sc_start(10 * dut.clk.period());
cycles+=10;
}
return cycles;
}
TEST_CASE("axi4_burst_alignment", "[AXI][pin-level]") {
@ -159,8 +147,9 @@ TEST_CASE("axi4_burst_alignment", "[AXI][pin-level]") {
unsigned resp_cnt{0};
} state;
run_scenario(state);
auto cycles = run_scenario(state);
REQUIRE(cycles<1000);
REQUIRE(sc_report_handler::get_count(SC_ERROR) == 0);
REQUIRE(sc_report_handler::get_count(SC_WARNING) == 0);
@ -169,17 +158,20 @@ TEST_CASE("axi4_burst_alignment", "[AXI][pin-level]") {
auto const& send_tx = e.second.first;
auto const& recv_tx = e.second.second;
REQUIRE(send_tx.size() == recv_tx.size());
for(auto i = 0; i<send_tx.size(); ++i)
for(auto i = 0; i<send_tx.size(); ++i) {
REQUIRE(send_tx[i]->get_response_status() == tlm::TLM_OK_RESPONSE);
CHECK(*send_tx[i] == *recv_tx[i]);
}
}
for(auto& e: state.read_tx) {
auto const& send_tx = e.second.first;
auto const& recv_tx = e.second.second;
REQUIRE(send_tx.size() == recv_tx.size());
for(auto i = 0; i<send_tx.size(); ++i)
for(auto i = 0; i<send_tx.size(); ++i){
REQUIRE(send_tx[i]->get_response_status() == tlm::TLM_OK_RESPONSE);
CHECK(*send_tx[i] == *recv_tx[i]);
}
}
}
@ -194,8 +186,9 @@ TEST_CASE("axi4_narrow_burst", "[AXI][pin-level]") {
unsigned resp_cnt{0};
} state;
run_scenario(state);
auto cycles = run_scenario(state);
REQUIRE(cycles<1000);
REQUIRE(sc_report_handler::get_count(SC_ERROR) == 0);
REQUIRE(sc_report_handler::get_count(SC_WARNING) == 0);