2022-10-02 08:14:58 +02:00
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#ifndef _TESTBENCH_H_
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#define _TESTBENCH_H_
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#include <axi/pe/axi_initiator.h>
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#include <axi/pe/simple_target.h>
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#include <axi/pin/axi4_initiator.h>
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#include <axi/pin/axi4_target.h>
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#include <axi/scv/recorder_modules.h>
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#include <scc.h>
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using namespace sc_core;
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using namespace axi;
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using namespace axi::pe;
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class testbench : public sc_core::sc_module {
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public:
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using bus_cfg = axi::axi4_cfg</*BUSWIDTH=*/64, /*ADDRWIDTH=*/32, /*IDWIDTH=*/4, /*USERWIDTH=*/1>;
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sc_core::sc_time clk_period{10, sc_core::SC_NS};
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sc_core::sc_clock clk{"clk", clk_period, 0.5, sc_core::SC_ZERO_TIME, true};
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sc_core::sc_signal<bool> rst{"rst"};
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// initiator side
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axi::axi_initiator_socket<bus_cfg::BUSWIDTH> intor{"intor"};
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axi::scv::axi_recorder_module<bus_cfg::BUSWIDTH> intor_rec{"intor_rec"};
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axi::pin::axi4_initiator<bus_cfg> intor_bfm{"intor_bfm"};
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// signal accurate bus
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2023-12-22 09:52:50 +01:00
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axi::aw_axi<bus_cfg, axi::signal_types> aw;
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axi::wdata_axi<bus_cfg, axi::signal_types> wdata;
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axi::b_axi<bus_cfg, axi::signal_types> b;
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axi::ar_axi<bus_cfg, axi::signal_types> ar;
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axi::rresp_axi<bus_cfg, axi::signal_types> rresp;
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2022-10-02 08:14:58 +02:00
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axi::pin::axi4_target<bus_cfg> tgt_bfm{"tgt_bfm"};
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// target side
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axi::scv::axi_recorder_module<bus_cfg::BUSWIDTH> tgt_rec{"tgt_rec"};
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axi::axi_target_socket<bus_cfg::BUSWIDTH> tgt{"tgt"};
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// engines
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axi::pe::axi_initiator<bus_cfg::BUSWIDTH> intor_pe;
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axi::pe::simple_target<bus_cfg::BUSWIDTH> tgt_pe;
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public:
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SC_HAS_PROCESS(testbench);
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2023-12-22 20:42:21 +01:00
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testbench()
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: testbench("testbench") {}
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2022-10-02 08:14:58 +02:00
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testbench(sc_core::sc_module_name nm)
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: sc_core::sc_module(nm)
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, intor_pe("intor_pe", intor)
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, tgt_pe("tgt_pe", tgt) {
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intor_pe.clk_i(clk);
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intor_bfm.clk_i(clk);
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tgt_bfm.clk_i(clk);
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tgt_pe.clk_i(clk);
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// pe socket to recorder
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intor(intor_rec.tsckt);
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// recorder to bfm
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intor_rec.isckt(intor_bfm.tsckt);
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// bfm to signals
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intor_bfm.bind_aw(aw);
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intor_bfm.bind_w(wdata);
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intor_bfm.bind_b(b);
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intor_bfm.bind_ar(ar);
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intor_bfm.bind_r(rresp);
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// signals to bfm
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tgt_bfm.bind_aw(aw);
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tgt_bfm.bind_w(wdata);
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tgt_bfm.bind_b(b);
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tgt_bfm.bind_ar(ar);
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tgt_bfm.bind_r(rresp);
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// bfm to recorder
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tgt_bfm.isckt(tgt_rec.tsckt);
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// recorder to target
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tgt_rec.isckt(tgt);
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}
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2023-12-22 20:42:21 +01:00
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void run1() {}
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2022-10-02 08:14:58 +02:00
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};
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#endif // _TESTBENCH_H_
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