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/*******************************************************************************
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* Copyright 2017 eyck@minres.com
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2017-09-25 22:00:46 +02:00
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*
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* Licensed under the Apache License, Version 2.0 (the "License"); you may not
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* use this file except in compliance with the License. You may obtain a copy
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* of the License at
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2017-09-25 22:00:46 +02:00
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*
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2017-09-20 21:26:46 +02:00
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations under
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* the License.
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******************************************************************************/
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#ifndef _PLIC_H_
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#define _PLIC_H_
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2017-10-04 15:16:52 +02:00
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#include <scc/register.h>
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#include <scc/tlm_target.h>
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namespace sysc {
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class plic_regs;
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class plic : public sc_core::sc_module, public scc::tlm_target<> {
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public:
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SC_HAS_PROCESS(plic);
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sc_core::sc_in<sc_core::sc_time> clk_i;
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sc_core::sc_in<bool> rst_i;
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sc_core::sc_vector<sc_core::sc_in<bool>> global_interrupts_i;
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sc_core::sc_out<bool> core_interrupt_o;
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sc_core::sc_event raise_int_ev;
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sc_core::sc_event clear_int_ev;
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plic(sc_core::sc_module_name nm);
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virtual ~plic();
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protected:
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void clock_cb();
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void reset_cb();
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2017-09-25 13:07:04 +02:00
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void init_callbacks();
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void global_int_port_cb();
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void handle_pending_int();
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void reset_pending_int(uint32_t irq);
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void raise_core_interrupt();
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void clear_core_interrupt();
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sc_core::sc_time clk;
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std::unique_ptr<plic_regs> regs;
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std::function<bool(scc::sc_register<uint32_t>, uint32_t)> m_claim_complete_write_cb;
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};
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} /* namespace sysc */
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#endif /* _PLIC_H_ */
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