2019-01-03 21:18:09 +01:00
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#ifndef TOP_H
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#define TOP_H
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#include <clkgen.h>
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#include <resetgen.h>
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#include <initiator.h>
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#include <target.h>
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#include <router.h>
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2020-10-08 17:45:57 +02:00
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enum { SLV_CNT=2};
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2019-01-03 21:18:09 +01:00
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SC_MODULE(Top) {
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ClkGen * clk_gen;
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ResetGen* reset_gen;
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Initiator* initiator;
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2020-10-08 17:45:57 +02:00
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Router<SLV_CNT>* router;
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Memory* memory[SLV_CNT];
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2019-01-03 21:18:09 +01:00
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Top(const sc_core::sc_module_name& nm)
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: sc_core::sc_module()
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, clk("clk")
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, reset("reset")
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{
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// Instantiate components
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clk_gen=new ClkGen("clk_gen");
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reset_gen=new ResetGen("reset_gen");
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initiator = new Initiator("initiator");
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2020-10-08 17:45:57 +02:00
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router = new Router<SLV_CNT>("router");
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for (int i = 0; i < SLV_CNT; i++) {
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2019-01-03 21:18:09 +01:00
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char txt[20];
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sprintf(txt, "memory_%d", i);
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memory[i] = new Memory(txt);
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}
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// Bind sockets
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initiator->socket.bind(router->target_socket);
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2020-10-08 17:45:57 +02:00
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for (int i = 0; i < SLV_CNT; i++)
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2019-01-03 21:18:09 +01:00
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router->initiator_socket[i].bind(memory[i]->socket);
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// connect signals
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clk_gen->clk_o(clk);
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reset_gen->reset_o(reset);
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initiator->clk_i(clk);
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initiator->reset_i(reset);
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router->clk_i(clk);
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router->reset_i(reset);
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for(auto& m: memory){
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m->clk_i(clk);
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m->reset_i(reset);
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}
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}
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sc_core::sc_signal<sc_core::sc_time> clk;
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sc_core::sc_signal<sc_dt::sc_logic> reset;
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};
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#endif
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