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ec0d2a7d7d
As per the RISC-V specification, time value can be obtained from a time CSR implemented in hardware or a MMIO based IP block. Qemu virt machine already supports timer csr while CLINT provides the timer for other platforms. Implement a hart specific timer feature that can be detected at runtime. As CSR based timer implementation are faster than MMIO address based, it is always preferred over MMIO based one. Signed-off-by: Atish Patra <atish.patra@wdc.com> Tested-by: Jonathan Balkind <jbalkind@cs.princeton.edu> Reviewed-by: Anup Patel <anup.patel@wdc.com>
52 lines
1.4 KiB
C
52 lines
1.4 KiB
C
/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2019 Western Digital Corporation or its affiliates.
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*
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* Authors:
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* Anup Patel <anup.patel@wdc.com>
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*/
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#ifndef __SBI_HART_H__
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#define __SBI_HART_H__
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#include <sbi/sbi_types.h>
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/** Possible feature flags of a hart */
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enum sbi_hart_features {
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/** Hart has PMP support */
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SBI_HART_HAS_PMP = (1 << 0),
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/** Hart has S-mode counter enable */
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SBI_HART_HAS_SCOUNTEREN = (1 << 1),
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/** Hart has M-mode counter enable */
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SBI_HART_HAS_MCOUNTEREN = (1 << 2),
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/** HART has timer csr implementation in hardware */
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SBI_HART_HAS_TIME = (1 << 3),
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};
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struct sbi_scratch;
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int sbi_hart_init(struct sbi_scratch *scratch, u32 hartid, bool cold_boot);
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extern void (*sbi_hart_expected_trap)(void);
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static inline ulong sbi_hart_expected_trap_addr(void)
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{
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return (ulong)sbi_hart_expected_trap;
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}
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void sbi_hart_delegation_dump(struct sbi_scratch *scratch);
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void sbi_hart_pmp_dump(struct sbi_scratch *scratch);
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int sbi_hart_pmp_check_addr(struct sbi_scratch *scratch, unsigned long daddr,
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unsigned long attr);
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bool sbi_hart_has_feature(u32 hartid, unsigned long feature);
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unsigned long sbi_hart_get_features(u32 hartid);
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void __attribute__((noreturn)) sbi_hart_hang(void);
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void __attribute__((noreturn))
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sbi_hart_switch_mode(unsigned long arg0, unsigned long arg1,
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unsigned long next_addr, unsigned long next_mode,
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bool next_virt);
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#endif
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