mirror of
https://github.com/riscv-software-src/opensbi.git
synced 2026-06-12 22:31:45 +01:00
Nicholas Piggin
a59c8fb9fb
The sbi_hart_pmp.c looks like a good place for the hart PMP CSR access functions. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260430045528.420437-9-npiggin@gmail.com Signed-off-by: Anup Patel <anup@brainfault.org>
275 lines
8.4 KiB
C
275 lines
8.4 KiB
C
/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2019 Western Digital Corporation or its affiliates.
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*
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* Authors:
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* Anup Patel <anup.patel@wdc.com>
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*/
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#include <sbi/riscv_asm.h>
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#include <sbi/riscv_encoding.h>
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#include <sbi/sbi_error.h>
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#include <sbi/sbi_platform.h>
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#include <sbi/sbi_console.h>
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#include <sbi/sbi_pmp.h>
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/* determine CPU extension, return non-zero support */
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int misa_extension_imp(char ext)
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{
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unsigned long misa = csr_read(CSR_MISA);
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if (misa) {
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if ('A' <= ext && ext <= 'Z')
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return misa & (1 << (ext - 'A'));
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if ('a' <= ext && ext <= 'z')
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return misa & (1 << (ext - 'a'));
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return 0;
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}
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return sbi_platform_misa_extension(sbi_platform_thishart_ptr(), ext);
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}
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int misa_xlen(void)
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{
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long r;
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if (csr_read(CSR_MISA) == 0)
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return sbi_platform_misa_xlen(sbi_platform_thishart_ptr());
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__asm__ __volatile__(
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"csrr t0, misa\n\t"
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"slti t1, t0, 0\n\t"
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"slli t1, t1, 1\n\t"
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"slli t0, t0, 1\n\t"
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"slti t0, t0, 0\n\t"
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"add %0, t0, t1"
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: "=r"(r)
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:
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: "t0", "t1");
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return r ? r : -1;
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}
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void misa_string(int xlen, char *out, unsigned int out_sz)
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{
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unsigned int i, pos = 0;
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const char valid_isa_order[] = "iemafdqclbjtpvnhkorwxyzg";
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if (!out)
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return;
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if (5 <= (out_sz - pos)) {
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out[pos++] = 'r';
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out[pos++] = 'v';
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switch (xlen) {
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case 1:
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out[pos++] = '3';
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out[pos++] = '2';
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break;
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case 2:
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out[pos++] = '6';
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out[pos++] = '4';
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break;
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case 3:
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out[pos++] = '1';
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out[pos++] = '2';
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out[pos++] = '8';
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break;
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default:
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sbi_panic("%s: Unknown misa.MXL encoding %d",
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__func__, xlen);
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return;
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}
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}
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for (i = 0; i < array_size(valid_isa_order) && (pos < out_sz); i++) {
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if (misa_extension_imp(valid_isa_order[i]))
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out[pos++] = valid_isa_order[i];
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}
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if (pos < out_sz)
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out[pos++] = '\0';
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}
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unsigned long csr_read_num(int csr_num)
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{
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#define switchcase_csr_read(__csr_num) \
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case __csr_num: \
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return csr_read(__csr_num);
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#define switchcase_csr_read_2(__csr_num) \
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switchcase_csr_read(__csr_num + 0) \
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switchcase_csr_read(__csr_num + 1)
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#define switchcase_csr_read_4(__csr_num) \
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switchcase_csr_read_2(__csr_num + 0) \
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switchcase_csr_read_2(__csr_num + 2)
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#define switchcase_csr_read_8(__csr_num) \
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switchcase_csr_read_4(__csr_num + 0) \
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switchcase_csr_read_4(__csr_num + 4)
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#define switchcase_csr_read_16(__csr_num) \
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switchcase_csr_read_8(__csr_num + 0) \
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switchcase_csr_read_8(__csr_num + 8)
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#define switchcase_csr_read_32(__csr_num) \
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switchcase_csr_read_16(__csr_num + 0) \
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switchcase_csr_read_16(__csr_num + 16)
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#define switchcase_csr_read_64(__csr_num) \
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switchcase_csr_read_32(__csr_num + 0) \
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switchcase_csr_read_32(__csr_num + 32)
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#define switchcase_csr_read_128(__csr_num) \
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switchcase_csr_read_64(__csr_num + 0) \
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switchcase_csr_read_64(__csr_num + 64)
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#define switchcase_csr_read_256(__csr_num) \
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switchcase_csr_read_128(__csr_num + 0) \
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switchcase_csr_read_128(__csr_num + 128)
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switch (csr_num) {
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switchcase_csr_read_16(CSR_PMPCFG0)
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switchcase_csr_read_64(CSR_PMPADDR0)
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switchcase_csr_read(CSR_MCYCLE)
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switchcase_csr_read(CSR_MINSTRET)
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switchcase_csr_read(CSR_MHPMCOUNTER3)
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switchcase_csr_read_4(CSR_MHPMCOUNTER4)
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switchcase_csr_read_8(CSR_MHPMCOUNTER8)
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switchcase_csr_read_16(CSR_MHPMCOUNTER16)
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switchcase_csr_read(CSR_MCOUNTINHIBIT)
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switchcase_csr_read(CSR_MCYCLECFG)
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switchcase_csr_read(CSR_MINSTRETCFG)
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switchcase_csr_read(CSR_MHPMEVENT3)
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switchcase_csr_read_4(CSR_MHPMEVENT4)
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switchcase_csr_read_8(CSR_MHPMEVENT8)
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switchcase_csr_read_16(CSR_MHPMEVENT16)
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#if __riscv_xlen == 32
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switchcase_csr_read(CSR_MCYCLEH)
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switchcase_csr_read(CSR_MINSTRETH)
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switchcase_csr_read(CSR_MHPMCOUNTER3H)
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switchcase_csr_read_4(CSR_MHPMCOUNTER4H)
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switchcase_csr_read_8(CSR_MHPMCOUNTER8H)
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switchcase_csr_read_16(CSR_MHPMCOUNTER16H)
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/**
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* The CSR range M[CYCLE, INSTRET]CFGH are available only if smcntrpmf
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* extension is present. The caller must ensure that.
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*/
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switchcase_csr_read(CSR_MCYCLECFGH)
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switchcase_csr_read(CSR_MINSTRETCFGH)
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/**
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* The CSR range MHPMEVENT[3-16]H are available only if sscofpmf
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* extension is present. The caller must ensure that.
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*/
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switchcase_csr_read(CSR_MHPMEVENT3H)
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switchcase_csr_read_4(CSR_MHPMEVENT4H)
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switchcase_csr_read_8(CSR_MHPMEVENT8H)
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switchcase_csr_read_16(CSR_MHPMEVENT16H)
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#endif
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switchcase_csr_read_256(CSR_CUSTOM0_U_RW_BASE)
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switchcase_csr_read_64(CSR_CUSTOM1_U_RO_BASE)
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switchcase_csr_read_64(CSR_CUSTOM2_S_RW_BASE)
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switchcase_csr_read_64(CSR_CUSTOM3_S_RW_BASE)
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switchcase_csr_read_64(CSR_CUSTOM4_S_RO_BASE)
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switchcase_csr_read_64(CSR_CUSTOM5_HS_RW_BASE)
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switchcase_csr_read_64(CSR_CUSTOM6_HS_RW_BASE)
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switchcase_csr_read_64(CSR_CUSTOM7_HS_RO_BASE)
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switchcase_csr_read_64(CSR_CUSTOM8_M_RW_BASE)
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switchcase_csr_read_64(CSR_CUSTOM9_M_RW_BASE)
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switchcase_csr_read_64(CSR_CUSTOM10_M_RO_BASE)
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default:
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sbi_panic("%s: Unknown CSR %#x", __func__, csr_num);
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return 0;
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}
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#undef switchcase_csr_read_256
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#undef switchcase_csr_read_128
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#undef switchcase_csr_read_64
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#undef switchcase_csr_read_32
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#undef switchcase_csr_read_16
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#undef switchcase_csr_read_8
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#undef switchcase_csr_read_4
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#undef switchcase_csr_read_2
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#undef switchcase_csr_read
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}
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void csr_write_num(int csr_num, unsigned long val)
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{
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#define switchcase_csr_write(__csr_num, __val) \
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case __csr_num: \
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csr_write(__csr_num, __val); \
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break;
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#define switchcase_csr_write_2(__csr_num, __val) \
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switchcase_csr_write(__csr_num + 0, __val) \
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switchcase_csr_write(__csr_num + 1, __val)
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#define switchcase_csr_write_4(__csr_num, __val) \
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switchcase_csr_write_2(__csr_num + 0, __val) \
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switchcase_csr_write_2(__csr_num + 2, __val)
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#define switchcase_csr_write_8(__csr_num, __val) \
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switchcase_csr_write_4(__csr_num + 0, __val) \
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switchcase_csr_write_4(__csr_num + 4, __val)
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#define switchcase_csr_write_16(__csr_num, __val) \
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switchcase_csr_write_8(__csr_num + 0, __val) \
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switchcase_csr_write_8(__csr_num + 8, __val)
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#define switchcase_csr_write_32(__csr_num, __val) \
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switchcase_csr_write_16(__csr_num + 0, __val) \
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switchcase_csr_write_16(__csr_num + 16, __val)
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#define switchcase_csr_write_64(__csr_num, __val) \
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switchcase_csr_write_32(__csr_num + 0, __val) \
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switchcase_csr_write_32(__csr_num + 32, __val)
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#define switchcase_csr_write_128(__csr_num, __val) \
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switchcase_csr_write_64(__csr_num + 0, __val) \
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switchcase_csr_write_64(__csr_num + 64, __val)
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#define switchcase_csr_write_256(__csr_num, __val) \
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switchcase_csr_write_128(__csr_num + 0, __val) \
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switchcase_csr_write_128(__csr_num + 128, __val)
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switch (csr_num) {
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switchcase_csr_write_16(CSR_PMPCFG0, val)
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switchcase_csr_write_64(CSR_PMPADDR0, val)
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switchcase_csr_write(CSR_MCYCLE, val)
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switchcase_csr_write(CSR_MINSTRET, val)
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switchcase_csr_write(CSR_MHPMCOUNTER3, val)
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switchcase_csr_write_4(CSR_MHPMCOUNTER4, val)
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switchcase_csr_write_8(CSR_MHPMCOUNTER8, val)
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switchcase_csr_write_16(CSR_MHPMCOUNTER16, val)
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#if __riscv_xlen == 32
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switchcase_csr_write(CSR_MCYCLEH, val)
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switchcase_csr_write(CSR_MINSTRETH, val)
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switchcase_csr_write(CSR_MHPMCOUNTER3H, val)
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switchcase_csr_write_4(CSR_MHPMCOUNTER4H, val)
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switchcase_csr_write_8(CSR_MHPMCOUNTER8H, val)
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switchcase_csr_write_16(CSR_MHPMCOUNTER16H, val)
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switchcase_csr_write(CSR_MCYCLECFGH, val)
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switchcase_csr_write(CSR_MINSTRETCFGH, val)
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switchcase_csr_write(CSR_MHPMEVENT3H, val)
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switchcase_csr_write_4(CSR_MHPMEVENT4H, val)
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switchcase_csr_write_8(CSR_MHPMEVENT8H, val)
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switchcase_csr_write_16(CSR_MHPMEVENT16H, val)
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#endif
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switchcase_csr_write(CSR_MCOUNTINHIBIT, val)
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switchcase_csr_write(CSR_MCYCLECFG, val)
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switchcase_csr_write(CSR_MINSTRETCFG, val)
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switchcase_csr_write(CSR_MHPMEVENT3, val)
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switchcase_csr_write_4(CSR_MHPMEVENT4, val)
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switchcase_csr_write_8(CSR_MHPMEVENT8, val)
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switchcase_csr_write_16(CSR_MHPMEVENT16, val)
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switchcase_csr_write_256(CSR_CUSTOM0_U_RW_BASE, val)
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switchcase_csr_write_64(CSR_CUSTOM2_S_RW_BASE, val)
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switchcase_csr_write_64(CSR_CUSTOM3_S_RW_BASE, val)
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switchcase_csr_write_64(CSR_CUSTOM5_HS_RW_BASE, val)
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switchcase_csr_write_64(CSR_CUSTOM6_HS_RW_BASE, val)
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switchcase_csr_write_64(CSR_CUSTOM8_M_RW_BASE, val)
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switchcase_csr_write_64(CSR_CUSTOM9_M_RW_BASE, val)
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default:
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sbi_panic("%s: Unknown CSR %#x", __func__, csr_num);
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break;
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}
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#undef switchcase_csr_write_256
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#undef switchcase_csr_write_128
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#undef switchcase_csr_write_64
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#undef switchcase_csr_write_32
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#undef switchcase_csr_write_16
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#undef switchcase_csr_write_8
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#undef switchcase_csr_write_4
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#undef switchcase_csr_write_2
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#undef switchcase_csr_write
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}
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