Simulatenous requests for tlbflush IPIs can have overlapping address
ranges.
Ignore if address range is same or within already existing fifo entries.
Update the tlb flush info in fifo directly if the one of the existing
entry lies within the new flush request.
Delete all entries if flush all request is recieved for the vma.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Implement a lock enabled iteration for fifo so that
caller can determine if next entry can be skipped or
any existing entries in fifo can be updated before enqueue.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Currently, there is no provision for tracking multiple IPIs sent
to a single hart at the same time by different harts.
Use a fifo manage the outstanding requests. While dequeueing, read all
the entries once, because we have only 1 bit to track the type of IPI.
Once the queue is full, busy wait until the there is space available in
queue. This is not the most elegant approach. It should be changed in
favor of a wakeup event once available in opensbi.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
OpenSBI should show error trace only if any valid SBI function
does not perform as expected.
However, OpenSBI should show notify the caller with a negative
error if given SBI function ID is not valid.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Scratch space setup needs to be done once for reboot for each
hart. _start_warm may be called several times if hart hotplug
is implemented.
Move scratch space setup to the beginning so that it is done
only once.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Currently, global page mappings are not flushed if start and size
arguments are zero.
Flush entire TLB if both size and start argument is passed as zero.
Fixes : 90cb491 (lib: Implement sfence.vma correctly)
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Currently, OpenSBI doesn't distinguish between sfence.vma
and sfence.vm asid calls. Moreover, it ignores the page
ranges and just flush entire TLB everytime.
Fix the sfence implementation by keeping all the tlb flush
info in scratch area.
The relevant Linux kernel code was added by
https://patchwork.kernel.org/project/linux-riscv/list/?series=89695
However, this patch is backward compatible with older version kernel
that doesn't have the above patches as well.
Fixes#87
Signed-off-by: Atish Patra <atish.patra@wdc.com>
A warm reset using reset button may put icache and registers
in non-coherent state.
Flush the icache and reset all registers for every hart.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
All the non-boot harts run in a tight loop which may cause a heavy load
on the memory bus. This may delay the boot hart to complete the cold boot
process.
Introduce few nop that will ease up the traffic.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
A warm reset by pressing the reset button may not initialize all the
registers to zero. Do it for every hart during warm boot.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
As per the current SBI specification, sbi_getc should return
an int instead of char.
In case of FIFO is empty, return -1 as per the specification.
Reported-by: Sergi Granell <xerpi.g.12@gmail.com>
Suggested-by:Thadeu Lima de Souza Cascardo <cascardo@cascardo.eti.br>
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Following updates to fu540 platform guide.
1. Update a section about flashing the firmware binary
to sdcard with correct partition identifier.
2. Refer the individual payload section.
3. Update uboot booting section.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Some older toolchains may not have all the csr's defined. Update all
the csr functions to use the CSR_ #define values instead of the
toolchain defined values.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Some older toolchains may not have all the csr's defined. Update all
the csr functions to use the CSR_ #define values instead of the
toolchain defined values.
Suggested-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Some older toolchains may not have all the csr's defined. Update all
the csr functions to use the CSR_ #define values instead of the
toolchain defined values.
Suggested-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Currently, only hart 1 is enabled for fu540 platform to support U-boot.
Introduce a compile time FU540_ENABLED_HART_MASK option so that specific
harts can be selected for booting. As fu540 is a multicore, we should
boot all cores by default except hart 0.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
As per the RISC-V ISA, mideleg and medeleg registers should not exist
if S-mode is not present for a hart.
We shouldn't access these CSRs if non S-mode harts.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
S-mode software may send IPI to self. For example,
tlbflush may be executed for the same hart.
Let the hart send IPI to itself. It's an overhead
but doesn't break anything. However, if we don't
allow it, it breaks if S-mode keep sending IPIs.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
IPIs are updated in scratch space by source hart.
However, different harts or same hart may want to
send different IPIs before previous IPI was read
by the target hart. Currently, previous IPI type
is overwritten in that case.
Use atomic bit set/clear operations to update IPIs.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
The secondary hart waits for an IPI signal from the boot hart to
executing boot code (hot boot). As a result, software generated
interrupts have to be enabled for secondary harts before waiting for
the boot hart boot completion IPI signal.
Enabling software generated interrupts (IPI) can be done independently
of the firmware code and moved to libsbi code so that the different
firmware do not have to implement this.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
PLIC DT entry fixup can be done by comparing external
interrupt number instead of context id. No need to invoke
fixup for each plic context.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Perform following DT updates.
1. Mask hart if mmu is not supported.
2. Add stdout-path under chosen node.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
There are couple of string function defined in platform
code. We no longer need them as we can directly link minimal
libc.
Every platform required to inclde this as PLIC driver required
libc functions.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Some of the platform (i.e. SiFive FU540) requires Device
Tree modification before it is passed to higher stages.
Add libfdt support now to help this process. Libfdt should
only be included per platform basis.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
As of now, uboot doesn't have support for SMP.
Moreover, unleashed board has a E51 hart which
doesn't not support S mode.
We should only boot only 1 non-zero hart.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
We should not jump to next stage if next mode (S-mode or U-mode)
is not supported by HART.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Anup Patel <anup.patel@wdc.com>
