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firmware: Add a barrier instruction for wait for boot hart

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Multi-core communication via memory requires the addition of a barrier
instructions to ensure cache coherency.

Signed-off-by: Xiang Wang <wxjstz@126.com>
This commit is contained in:
Xiang Wang
2019-03-04 17:22:37 +08:00
committed by Anup Patel
parent 1c87f0f9b1
commit 05602e2bf4
1 changed files with 1 additions and 0 deletions
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firmware/fw_base.S
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@@ -114,6 +114,7 @@ _fdt_reloc_done:
/* Wait for boot hart */
_wait_for_boot_hart:
fence rw, rw
la a4, _boot_hart_done
REG_L a5, (a4)
beqz a5, _wait_for_boot_hart