Vladimir Kondratiev
9169290ca9
platform: generic: mips eyeq7h: fix NCORE registers access from clusters 1..2
...
CPU clusters 1 and 2 cannot access NCORE registers through AUX ports.
AUX ports of clusters 1 and 2 are connected to NCORE through east port.
East port has no access to NCORE registers address space.
Re-route NCORE registers range to MEM port by re-configuring MMIO
regions in the GCR. REsulting map is as below. Mind a gap between
regions [1] and [2]; this gap covering NCORE registers now routed
to the default MEM port
Cluster 0: 4 MMIO regions
[0] : 0x0000000000000000-0x000000001fff0000 AUX0 UC|UCA
[1] : 0x0000000020000000-0x00000000677f0000 AUX0 ANY
[2] : 0x0000000080000000-0x0000001fffff0000 AUX0 UC|UCA
[3] : --disabled--
Cluster 1: 4 MMIO regions
[0] : 0x0000000000000000-0x000000001fff0000 AUX0 UC|UCA
[1] : 0x0000000020000000-0x00000000677f0000 AUX0 ANY
[2] : 0x0000000080000000-0x0000001fffff0000 AUX0 UC|UCA
[3] : --disabled--
Cluster 2: 4 MMIO regions
[0] : 0x0000000000000000-0x000000001fff0000 AUX0 UC|UCA
[1] : 0x0000000020000000-0x00000000677f0000 AUX0 ANY
[2] : 0x0000000080000000-0x0000001fffff0000 AUX0 UC|UCA
[3] : --disabled--
Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com >
Reviewed-by: Anup Patel <anup@brainfault.org >
Link: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-19-621d004d1a21@mobileye.com
Signed-off-by: Anup Patel <anup@brainfault.org >
2026-02-25 18:49:03 +05:30
Vladimir Kondratiev
2ca2e0caf0
platform: generic: mips eyeq7h: synchronize timers across clusters
...
Use eyeq7 specific method to synchronously restart architectural
mtimer and eyeq7h specific high-resolution timer with common
hardware trigger. This ensures all timers are precisely in sync
Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com >
Reviewed-by: Anup Patel <anup@brainfault.org >
Link: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-18-621d004d1a21@mobileye.com
Signed-off-by: Anup Patel <anup@brainfault.org >
2026-02-25 18:49:03 +05:30
Vladimir Kondratiev
76ecd8f37a
platform: generic: mips p8700: use SBI bitfield manipulator macros
...
Switch to GENMASK, EXTRACT_BITFIELD, INSERT_BITFIELD
Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com >
Reviewed-by: Anup Patel <anup@brainfault.org >
Link: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-16-621d004d1a21@mobileye.com
Signed-off-by: Anup Patel <anup@brainfault.org >
2026-02-25 18:49:03 +05:30
Vladimir Kondratiev
bdec423074
platform: generic: mips p8700: CPU clusters memranges
...
Reserve memory regions for CPU clusters according to P8700
cluster memory layout.
There's a set of components in the CPU cluster according to [1]
[1] https://mips.com/wp-content/uploads/2025/11/P8700-F_Programmers_Reference_Manual-TM.pdf
Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com >
Reviewed-by: Anup Patel <anup@brainfault.org >
Link: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-15-621d004d1a21@mobileye.com
Signed-off-by: Anup Patel <anup@brainfault.org >
2026-02-25 18:49:03 +05:30
Vladimir Kondratiev
df7bbe7c2e
platform: generic: mips p8700: cache geometry detection
...
P8700 has a read-only cache configuration registers.
Provide a CPU specific function to extract cache information.
Use this information in the eyeq7h board for informational
message
Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com >
Reviewed-by: Anup Patel <anup@brainfault.org >
Link: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-14-621d004d1a21@mobileye.com
Signed-off-by: Anup Patel <anup@brainfault.org >
2026-02-25 18:49:03 +05:30
Vladimir Kondratiev
8935f79c95
platform: generic: mips eyeq7h: deassert accelerator cluster resets
...
On the EyeQ7H board, there's cluster level resets found in the
accelerator OLBs. These resets should be deasserted once on boot
and never used after
Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com >
Reviewed-by: Anup Patel <anup@brainfault.org >
Link: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-13-621d004d1a21@mobileye.com
Signed-off-by: Anup Patel <anup@brainfault.org >
2026-02-25 18:49:03 +05:30
Vladimir Kondratiev
ee553291d8
platform: generic: mips eyeq7h: detect accelerators cluster presence
...
In the design, accelerator clusters ACC[01] and XNN[01] presence
indicated by the OLB_WEST register OLB_WEST_TSTCSR.
In the simulation environments, part (or all) accelerators may be
not instantiated
Disable clusters not present in the model, updating the DTB
Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com >
Reviewed-by: Anup Patel <anup@brainfault.org >
Link: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-12-621d004d1a21@mobileye.com
Signed-off-by: Anup Patel <anup@brainfault.org >
2026-02-25 18:49:03 +05:30
Vladimir Kondratiev
26748d7e12
platform: generic: mips eyeq7h: power up clusters with OLB
...
In the eyeq7h platform, there's extra power control for the CPU
clusters. To enable cluster, it should be powered up using this OLB
registers prior to accessing any cluster management registers
Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com >
Reviewed-by: Anup Patel <anup@brainfault.org >
Link: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-11-621d004d1a21@mobileye.com
Signed-off-by: Anup Patel <anup@brainfault.org >
2026-02-25 18:49:03 +05:30
Vladimir Kondratiev
79dfc3a868
platform: generic: mips: add P8700 based "eyeq7h" and "boston"
...
Refactor MIPS P8700 support, convert P8700 into a "CPU" and add
2 platforms using this CPU:
- "boston" - FPGA platform developed by MIPS
- "eyeq7h" - automotive platform by Mobileye
Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com >
Reviewed-by: Anup Patel <anup@brainfault.org >
Link: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-10-621d004d1a21@mobileye.com
Signed-off-by: Anup Patel <anup@brainfault.org >
2026-02-25 18:49:03 +05:30
