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platform: generic: mips eyeq7h: synchronize timers across clusters

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Use eyeq7 specific method to synchronously restart architectural
mtimer and eyeq7h specific high-resolution timer with common
hardware trigger. This ensures all timers are precisely in sync

Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Link: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-18-621d004d1a21@mobileye.com
Signed-off-by: Anup Patel <anup@brainfault.org>
This commit is contained in:
Vladimir Kondratiev
2026-02-23 16:54:57 +02:00
committed by Anup Patel
parent a3aeef7c14
commit 2ca2e0caf0
3 changed files with 23 additions and 0 deletions
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1
platform/generic/include/mips/mips-cm.h
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@@ -76,6 +76,7 @@ CPC_CX_ACCESSOR_RW(32, CPC_Cx_STAT_CONF, stat_conf)
CPS_ACCESSOR_RW(cpc, sz, CPC_OFFSET + (off), name)
CPC_ACCESSOR_RW(32, CPC_PWRUP_CTL, pwrup_ctl)
CPC_ACCESSOR_RW(64, CPC_TIMECTL, timectl)
CPC_ACCESSOR_RW(64, CPC_HRTIME, hrtime)
CPC_ACCESSOR_RW(32, CPC_CM_STAT_CONF, cm_stat_conf)

5
platform/generic/include/mips/p8700.h
View File

@@ -147,6 +147,11 @@ extern const struct p8700_cm_info *p8700_cm_info;
/* CPC Block offsets */
#define CPC_PWRUP_CTL 0x0030
#define CPC_TIMECTL 0x0058
#define TIMECTL_HARMED BIT(3)
#define TIMECTL_HSTOP BIT(2)
#define TIMECTL_MARMED BIT(1)
#define TIMECTL_MSTOP BIT(0)
#define CPC_HRTIME 0x0090
#define CPC_CM_STAT_CONF 0x1008

17
platform/generic/mips/eyeq7h.c
View File

@@ -44,6 +44,9 @@
#define TSTCSR_MIPS12_PRESENT GENMASK(3, 2)
#define TSTCSR_ACC_PRESENT GENMASK(5, 4)
#define OLB_WEST_CFG 0x68
#define WEST_CFG_MIPS_MTIME_START BIT(8)
/* Use in nascent init - not have DTB yet */
#define DRAM_ADDRESS 0x800000000UL
#define DRAM_SIZE 0x800000000UL
@@ -243,6 +246,20 @@ static void eyeq7h_init_clusters(void)
eyeq7h_power_up_other_cluster(INSERT_FIELD(0, P8700_HARTID_CLUSTER, i));
}
eyeq7h_active_clusters = num_clusters;
/**
* sync timers in all clusters. EQ7 have counters restart pins for clusters
* connected to the OLB.
* Stop/arm all counters, then restart all at once
*/
for (int i = 0; i < num_clusters; i++) {
write_cpc_timectl(INSERT_FIELD(0, P8700_HARTID_CLUSTER, i),
TIMECTL_HARMED | TIMECTL_HSTOP | TIMECTL_MARMED | TIMECTL_MSTOP);
}
{
u32 cfg = readl((void*)OLB_WEST + OLB_WEST_CFG);
writel(cfg | WEST_CFG_MIPS_MTIME_START, (void*)OLB_WEST + OLB_WEST_CFG);
}
}
static int eyeq7h_early_init(bool cold_boot)