Mirrors/opensbi
4
0
Fork 1
mirror of https://github.com/riscv-software-src/opensbi.git synced 2026-02-27 18:01:45 +00:00
Code Issues Packages Projects Releases Wiki Activity

platform: generic: mips eyeq7h: fix NCORE registers access from clusters 1..2

Browse Source 
CPU clusters 1 and 2 cannot access NCORE registers through AUX ports.
AUX ports of clusters 1 and 2 are connected to NCORE through east port.
East port has no access to NCORE registers address space.

Re-route NCORE registers range to MEM port by re-configuring MMIO
regions in the GCR. REsulting map is as below. Mind a gap between
regions [1] and [2]; this gap covering NCORE registers now routed
to the default MEM port
Cluster 0: 4 MMIO regions
  [0] : 0x0000000000000000-0x000000001fff0000 AUX0 UC|UCA
  [1] : 0x0000000020000000-0x00000000677f0000 AUX0    ANY
  [2] : 0x0000000080000000-0x0000001fffff0000 AUX0 UC|UCA
  [3] : --disabled--
Cluster 1: 4 MMIO regions
  [0] : 0x0000000000000000-0x000000001fff0000 AUX0 UC|UCA
  [1] : 0x0000000020000000-0x00000000677f0000 AUX0    ANY
  [2] : 0x0000000080000000-0x0000001fffff0000 AUX0 UC|UCA
  [3] : --disabled--
Cluster 2: 4 MMIO regions
  [0] : 0x0000000000000000-0x000000001fff0000 AUX0 UC|UCA
  [1] : 0x0000000020000000-0x00000000677f0000 AUX0    ANY
  [2] : 0x0000000080000000-0x0000001fffff0000 AUX0 UC|UCA
  [3] : --disabled--

Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Link: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-19-621d004d1a21@mobileye.com
Signed-off-by: Anup Patel <anup@brainfault.org>
This commit is contained in:
Vladimir Kondratiev
2026-02-23 16:54:58 +02:00
committed by Anup Patel
parent 2ca2e0caf0
commit 9169290ca9
2 changed files with 25 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

18
platform/generic/include/mips/p8700.h
View File

@@ -144,6 +144,24 @@ extern const struct p8700_cm_info *p8700_cm_info;
#define L2SM_COP_RESULT_ABORT_OK 3
#define L2SM_COP_RESULT_ABORT_ERROR 4
#define GCR_L2SM_COP_PRESENT BIT(31)
/* MMIO regions. Actual count in GCR_GLOBAL_CONFIG.GCR_GC_NUM_MMIOS */
#define GCR_MMIO_BOTTOM(n) (0x700 + (n) * 0x10) /* n = 0..7 */
#define GCR_MMIO_TOP(n) (0x708 + (n) * 0x10) /* n = 0..7 */
#define GCR_MMIO_ADDR GENMASK(47, 16) /* both top and bottom */
#define GCR_MMIO_BOTTOM_CCA GENMASK(9, 8)
#define GCR_MMIO_BOTTOM_FORCE_NC BIT(6)
/*
* 15:12 - reserved
* 11 - AUX3
* 10 - AUX2
* 9 - AUX1
* 8 - AUX0
* 7:1 - reserved
* 0 - Main memory port; MEM
*/
#define GCR_MMIO_BOTTOM_PORT GENMASK(5, 2)
#define GCR_MMIO_BOTTOM_DIS_RQ_LIM BIT(1)
#define GCR_MMIO_BOTTOM_EN BIT(0)
/* CPC Block offsets */
#define CPC_PWRUP_CTL 0x0030

7
platform/generic/mips/eyeq7h.c
View File

@@ -37,6 +37,7 @@
#define OLB_ACC1 0x65000000
#define OLB_XNN0 0x43600000
#define OLB_XNN1 0x63600000
#define NCORE 0x67800000
#define OLB_WEST 0x48600000
#define OLB_WEST_TSTCSR 0x60
#define TSTCSR_PALLADIUM BIT(0)
@@ -369,6 +370,12 @@ static int eyeq7h_nascent_init(void)
(void *)(cm_base + L2_PFT_CONTROL_OFFSET));
__raw_writel(0x15ff,
(void *)(cm_base + L2_PFT_CONTROL_B_OFFSET));
/*
* Remove access to NCORE CSRs from mmio region 1
* which is routed to AUX. NCORE to use default route through MEM.
*/
__raw_writeq(NCORE-1, (void *)(cm_base + GCR_MMIO_TOP(1)));
mb();
}
/* Per core set up */