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Author SHA1 Message Date
Xiang WangandAnup Patel 05602e2bf4 firmware: Add a barrier instruction for wait for boot hart 
Multi-core communication via memory requires the addition of a barrier
instructions to ensure cache coherency.

Signed-off-by: Xiang Wang <wxjstz@126.com>
 2019-03-05 09:09:40 +05:30
Xiang WangandAnup Patel 1c87f0f9b1 firmware: Move _boot_hart_done to the data section 
Writable code section can cause some security problems, so move _boot_hart_done
to the data section

Signed-off-by: Xiang Wang <wxjstz@126.com>
 2019-03-05 09:09:40 +05:30
Xiang WangandAnup Patel a72467f574 Add tags to .gitignore for being development friendly 
Signed-off-by: Xiang Wang <wxjstz@126.com>
 2019-03-05 09:07:23 +05:30