Commit Graph
10 Commits
Author SHA1 Message Date
Xiang WandAnup Patel 4ef2f5d3e6 firware: optimize the exception exit code
There are two copies of the same abnormal exit code, this patch deletes one

Signed-off-by: Xiang W <wxjstz@126.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
2021-04-01 10:48:35 +05:30
Xiang WandAnup Patel 813f7f4c25 lib: Add error detection for misa_extension
Add assertions for misa_extension to prevent incoming illegal
characters.

Signed-off-by: Xiang Wang <merle@hardenedlinux.org>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
2019-11-27 12:10:33 +05:30
Xiang WandAnup Patel 65aa5873c3 firmware: Handle overlapping load and link addresses in relocation
The old code may corrupt the code of the waiting hart hence this patch
keeps waiting HART within relocation code range at time of relocation.

Signed-off-by: Xiang W <wxjstz@126.com>
Acked-by: Anup Patel <anup.patel@wdc.com>
2019-06-24 09:39:18 +05:30
Xiang WandAnup Patel a5b37bd7d2 firmware: Handle overlapping load and link addresses in relocation
This patch extends relocation to handle overlapping load and link
addresses.

The updated relocation will work fine in most cases except when the
relocate copy loop itself falls in overlapping load and link addresses.

Signed-off-by: Xiang W <wxjstz@126.com>
Signed-off-by: Anup Patel <anup.patel@wdc.com>
2019-06-17 11:53:42 +05:30
Xiang WangandAlistair Francis c1d01b0c2e platform/common/libfdt: fix unnecessary multiple inclusions
Signed-off-by: Xiang Wang <wxjstz@126.com>
2019-04-25 10:23:31 -07:00
Xiang WangandAnup Patel 09f976802b firmware: Fix source fdt alignment
When I tried to start opensbi with coreboot, I found that aligning to a 16-byte
boundary would make a copy error.

Corrected to align to an machine word length boundary.

Signed-off-by: Xiang Wang <wxjstz@126.com>
2019-04-04 09:10:28 +05:30
Xiang WangandAtish Patra 9eb8f0f90d platform: Make the platform read-only
platform should be a read-only variable, if it is placed in the data
segment, it may be exploited.

Signed-off-by: Xiang Wang <wxjstz@126.com>
2019-03-06 11:10:35 -08:00
Xiang WangandAnup Patel 05602e2bf4 firmware: Add a barrier instruction for wait for boot hart
Multi-core communication via memory requires the addition of a barrier
instructions to ensure cache coherency.

Signed-off-by: Xiang Wang <wxjstz@126.com>
2019-03-05 09:09:40 +05:30
Xiang WangandAnup Patel 1c87f0f9b1 firmware: Move _boot_hart_done to the data section
Writable code section can cause some security problems, so move _boot_hart_done
to the data section

Signed-off-by: Xiang Wang <wxjstz@126.com>
2019-03-05 09:09:40 +05:30
Xiang WangandAnup Patel a72467f574 Add tags to .gitignore for being development friendly
Signed-off-by: Xiang Wang <wxjstz@126.com>
2019-03-05 09:07:23 +05:30