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platform: generic: eyeq7h: enable ECC on L1 cache

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Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com>
Link: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-23-621d004d1a21@mobileye.com
Signed-off-by: Anup Patel <anup@brainfault.org>
This commit is contained in:
Vladimir Kondratiev
2026-02-23 16:55:02 +02:00
committed by Anup Patel
parent f07be546e5
commit 8d1c21b387
1 changed files with 2 additions and 0 deletions
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platform/generic/mips/eyeq7h.c
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@@ -436,6 +436,8 @@ static int eyeq7h_nascent_init(void)
/* Per hart set up */
/* Enable AMO and RDTIME illegal instruction exceptions. */
csr_set(CSR_MIPSCONFIG6, (1<<2)|(1<<1));
/* enable ECC for L1 I/D and FTLB */
csr_set(CSR_MIPSERRCTL, MIPSERRCTL_PE);
return 0;
}