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platform: generic/andes: pair non-retentive CSR save/restore with a flag

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The restore was gated on sbi_init_count() and the current sleep type,
which is only a proxy for "did this hart actually save its CSRs". Track
it explicitly instead, so restore is self-guarding and the call site
needs no conditions.

Signed-off-by: Ben Zong-You Xie <ben717@andestech.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Link: https://lore.kernel.org/r/20260728081041.2724668-4-ben717@andestech.com
Signed-off-by: Anup Patel <anup@brainfault.org>
This commit is contained in:
Ben Zong-You Xie
2026-09-01 10:46:23 +05:30
committed by Anup Patel
parent 4c5d9d9f93
commit 733867c0c8
2 changed files with 15 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files
platform/generic/andes/ae350.c
+12 -6
View File
@@ -34,6 +34,8 @@ void ae350_non_ret_save(struct sbi_scratch *scratch)
andes_hdata->pmacfg2 = csr_read_num(CSR_PMACFG0 + 2);
for (int i = 0; i < 16; i++)
andes_hdata->pmaaddrX[i] = csr_read_num(CSR_PMAADDR0 + i);
andes_hdata->saved = true;
}
void ae350_non_ret_restore(struct sbi_scratch *scratch)
@@ -41,6 +43,9 @@ void ae350_non_ret_restore(struct sbi_scratch *scratch)
struct andes_hart_data *andes_hdata = sbi_scratch_offset_ptr(scratch,
andes_hart_data_offset);
if (!andes_hdata->saved)
return;
csr_write(CSR_MCACHE_CTL, andes_hdata->mcache_ctl);
csr_write(CSR_MMISC_CTL, andes_hdata->mmisc_ctl);
csr_write(CSR_MPFT_CTL, andes_hdata->mpft_ctl);
@@ -52,6 +57,8 @@ void ae350_non_ret_restore(struct sbi_scratch *scratch)
csr_write_num(CSR_PMACFG0 + 2, andes_hdata->pmacfg2);
for (int i = 0; i < 16; i++)
csr_write_num(CSR_PMAADDR0 + i, andes_hdata->pmaaddrX[i]);
andes_hdata->saved = false;
}
void ae350_enable_coherency_warmboot(void)
@@ -62,18 +69,17 @@ void ae350_enable_coherency_warmboot(void)
static int ae350_early_init(bool cold_boot)
{
u32 hartid = current_hartid();
u32 sleep_type = atcsmu_get_sleep_type(hartid);
if (cold_boot) {
andes_hart_data_offset = sbi_scratch_alloc_offset(sizeof(struct andes_hart_data));
if (!andes_hart_data_offset)
return SBI_ENOMEM;
}
/* Don't restore Andes CSRs during boot or wake up from light sleep */
if (sbi_init_count(current_hartindex()) && sleep_type == SBI_SUSP_SLEEP_TYPE_SUSPEND)
ae350_non_ret_restore(sbi_scratch_thishart_ptr());
/*
* This is a no-op unless this hart actually saved them, so it is safe
* to call on every path.
*/
ae350_non_ret_restore(sbi_scratch_thishart_ptr());
return generic_early_init(cold_boot);
}
platform/generic/include/andes/andes.h
+3
View File
@@ -96,6 +96,9 @@ struct andes_hart_data {
unsigned long pmacfg0;
unsigned long pmacfg2;
unsigned long pmaaddrX[16];
/* Set when the CSRs above hold a saved copy awaiting restore */
bool saved;
};
void ae350_non_ret_save(struct sbi_scratch *scratch);