mirror of
https://github.com/riscv-software-src/opensbi.git
synced 2026-09-08 18:21:29 +01:00
Ben Zong-You Xie
733867c0c8
The restore was gated on sbi_init_count() and the current sleep type, which is only a proxy for "did this hart actually save its CSRs". Track it explicitly instead, so restore is self-guarding and the call site needs no conditions. Signed-off-by: Ben Zong-You Xie <ben717@andestech.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260728081041.2724668-4-ben717@andestech.com Signed-off-by: Anup Patel <anup@brainfault.org>
106 lines
3.0 KiB
C
106 lines
3.0 KiB
C
/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2025 Andes Technology Corporation
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*/
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#include <andes/andes.h>
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#include <andes/andes_pmu.h>
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#include <andes/andes_sbi.h>
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#include <platform_override.h>
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#include <sbi/sbi_ecall_interface.h>
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#include <sbi/riscv_asm.h>
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#include <sbi/sbi_init.h>
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#include <sbi/sbi_scratch.h>
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#include <sbi_utils/fdt/fdt_helper.h>
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#include <sbi_utils/hsm/fdt_hsm_andes_atcsmu.h>
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static unsigned long andes_hart_data_offset;
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extern void _start_warm(void);
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void ae350_non_ret_save(struct sbi_scratch *scratch)
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{
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struct andes_hart_data *andes_hdata = sbi_scratch_offset_ptr(scratch,
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andes_hart_data_offset);
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andes_hdata->mcache_ctl = csr_read(CSR_MCACHE_CTL);
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andes_hdata->mmisc_ctl = csr_read(CSR_MMISC_CTL);
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andes_hdata->mpft_ctl = csr_read(CSR_MPFT_CTL);
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andes_hdata->mslideleg = csr_read(CSR_MSLIDELEG);
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andes_hdata->mxstatus = csr_read(CSR_MXSTATUS);
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andes_hdata->slie = csr_read(CSR_SLIE);
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andes_hdata->slip = csr_read(CSR_SLIP);
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andes_hdata->pmacfg0 = csr_read(CSR_PMACFG0);
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andes_hdata->pmacfg2 = csr_read_num(CSR_PMACFG0 + 2);
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for (int i = 0; i < 16; i++)
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andes_hdata->pmaaddrX[i] = csr_read_num(CSR_PMAADDR0 + i);
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andes_hdata->saved = true;
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}
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void ae350_non_ret_restore(struct sbi_scratch *scratch)
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{
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struct andes_hart_data *andes_hdata = sbi_scratch_offset_ptr(scratch,
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andes_hart_data_offset);
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if (!andes_hdata->saved)
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return;
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csr_write(CSR_MCACHE_CTL, andes_hdata->mcache_ctl);
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csr_write(CSR_MMISC_CTL, andes_hdata->mmisc_ctl);
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csr_write(CSR_MPFT_CTL, andes_hdata->mpft_ctl);
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csr_write(CSR_MSLIDELEG, andes_hdata->mslideleg);
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csr_write(CSR_MXSTATUS, andes_hdata->mxstatus);
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csr_write(CSR_SLIE, andes_hdata->slie);
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csr_write(CSR_SLIP, andes_hdata->slip);
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csr_write(CSR_PMACFG0, andes_hdata->pmacfg0);
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csr_write_num(CSR_PMACFG0 + 2, andes_hdata->pmacfg2);
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for (int i = 0; i < 16; i++)
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csr_write_num(CSR_PMAADDR0 + i, andes_hdata->pmaaddrX[i]);
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andes_hdata->saved = false;
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}
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void ae350_enable_coherency_warmboot(void)
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{
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ae350_enable_coherency();
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_start_warm();
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}
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static int ae350_early_init(bool cold_boot)
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{
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if (cold_boot) {
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andes_hart_data_offset = sbi_scratch_alloc_offset(sizeof(struct andes_hart_data));
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if (!andes_hart_data_offset)
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return SBI_ENOMEM;
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}
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/*
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* This is a no-op unless this hart actually saved them, so it is safe
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* to call on every path.
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*/
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ae350_non_ret_restore(sbi_scratch_thishart_ptr());
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return generic_early_init(cold_boot);
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}
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static int ae350_platform_init(const void *fdt, int nodeoff, const struct fdt_match *match)
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{
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generic_platform_ops.early_init = ae350_early_init;
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generic_platform_ops.extensions_init = andes_pmu_extensions_init;
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generic_platform_ops.pmu_init = andes_pmu_init;
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generic_platform_ops.vendor_ext_provider = andes_sbi_vendor_ext_provider;
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return 0;
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}
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static const struct fdt_match andes_ae350_match[] = {
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{ .compatible = "andestech,ae350" },
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{ },
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};
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const struct fdt_driver andes_ae350 = {
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.match_table = andes_ae350_match,
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.init = ae350_platform_init,
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};
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