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platform: generic: mips eyeq7h: synchronize timers across clusters

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Use eyeq7 specific method to synchronously restart architectural
mtimer and eyeq7h specific high-resolution timer with common
hardware trigger. This ensures all timers are precisely in sync

Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Link: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-18-621d004d1a21@mobileye.com
Signed-off-by: Anup Patel <anup@brainfault.org>
This commit is contained in:
Vladimir Kondratiev
2026-02-23 16:54:57 +02:00
committed by Anup Patel
parent a3aeef7c14
commit 2ca2e0caf0
3 changed files with 23 additions and 0 deletions
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1
platform/generic/include/mips/mips-cm.h
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@@ -76,6 +76,7 @@ CPC_CX_ACCESSOR_RW(32, CPC_Cx_STAT_CONF, stat_conf)
CPS_ACCESSOR_RW(cpc, sz, CPC_OFFSET + (off), name)
CPC_ACCESSOR_RW(32, CPC_PWRUP_CTL, pwrup_ctl)
CPC_ACCESSOR_RW(64, CPC_TIMECTL, timectl)
CPC_ACCESSOR_RW(64, CPC_HRTIME, hrtime)
CPC_ACCESSOR_RW(32, CPC_CM_STAT_CONF, cm_stat_conf)

5
platform/generic/include/mips/p8700.h
View File

@@ -147,6 +147,11 @@ extern const struct p8700_cm_info *p8700_cm_info;
/* CPC Block offsets */
#define CPC_PWRUP_CTL 0x0030
#define CPC_TIMECTL 0x0058
#define TIMECTL_HARMED BIT(3)
#define TIMECTL_HSTOP BIT(2)
#define TIMECTL_MARMED BIT(1)
#define TIMECTL_MSTOP BIT(0)
#define CPC_HRTIME 0x0090
#define CPC_CM_STAT_CONF 0x1008