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Mirrors/RISCV-VP
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mirror of https://github.com/Minres/RISCV-VP.git synced 2025-12-17 17:01:35 +00:00
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57 Commits 4 Branches 0 Tags
586b9cb77e6eeb81b8fdcd97bd4cc659a709b6d8
Commit Graph

9 Commits

Author SHA1 Message Date
Eyck Jentzsch
7cb270a65b updates submodules 2025-11-07 11:52:36 +01:00
Eyck Jentzsch
3ef72aa434 updates dnt-rise-riscv 2025-09-16 07:50:29 +02:00
Eyck Jentzsch
68d6aab4c5 updates dbt-rise-riscv 2025-09-15 20:54:39 +02:00
Eyck Jentzsch
8581509357 adds standalone FW Debug launch 2025-09-14 14:57:26 +02:00
Eyck Jentzsch
dc71178c0c fixes dgb access for 64bit cores 2025-08-14 15:53:23 +02:00
Eyck Jentzsch
d6a71a2065 updates submodules and setup files 2025-08-08 09:36:34 +02:00
Eyck Jentzsch
b29f7ab6fa make BSP location for fw configurable 2025-07-30 06:41:36 +02:00
Eyck Jentzsch
7327ca4fb0 updates memory map and prebuilt fw 2025-07-30 06:39:17 +02:00
Eyck Jentzsch
c15fd95d4c updates README.md, FW, some names and does some cleanup 2024-06-30 20:22:19 +02:00
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