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https://github.com/Minres/RISCV-VP.git
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updates dbt-rise-riscv and vpvper
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Submodule dbt-rise-riscv updated: 3678067320...4990d15a35
2
scc
2
scc
Submodule scc updated: 3f5d963ae0...c54fc1b084
@@ -5,7 +5,6 @@
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*/
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#include "system.h"
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#include <minres/timer.h>
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#include <minres/uart.h>
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#include <scc/utilities.h>
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@@ -57,9 +56,9 @@ system::system(sc_core::sc_module_name nm)
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aclint.mtime_clk_i(mtime_clk);
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aclint.mtime_o(mtime_s);
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aclint.mtime_int_o(mtime_int_s);
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aclint.msip_int_o(msip_int_s);
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irq_ctrl.irq_o(core_int_s);
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aclint.mtime_int_o[0](clint_int_s[sysc::riscv::TIMER_IRQ]);
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aclint.msip_int_o[0](clint_int_s[sysc::riscv::SW_IRQ]);
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irq_ctrl.irq_o(clint_int_s[sysc::riscv::EXT_IRQ]);
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irq_ctrl.pending_irq_i(irq_int_s);
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uart0.irq_o(irq_int_s[0]);
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@@ -68,10 +67,7 @@ system::system(sc_core::sc_module_name nm)
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qspi.irq_o(irq_int_s[3]);
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core_complex.mtime_i(mtime_s);
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core_complex.timer_irq_i(mtime_int_s);
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core_complex.ext_irq_i(core_int_s);
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core_complex.local_irq_i(local_int_s);
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core_complex.sw_irq_i(msip_int_s);
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core_complex.clint_irq_i(clint_int_s);
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gpio0.pins_i(pins_i);
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gpio0.pins_o(pins_o);
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@@ -63,10 +63,10 @@ private:
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scc::memory<8_kB, scc::LT> boot_rom{"boot_rom"};
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sc_core::sc_signal<sc_core::sc_time> mtime_clk{"mtime_clk"};
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sc_core::sc_signal<bool, sc_core::SC_MANY_WRITERS> rst_s{"rst_s"}, mtime_int_s{"mtime_int_s"}, msip_int_s{"msip_int_s"};
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sc_core::sc_signal<bool, sc_core::SC_MANY_WRITERS> rst_s{"rst_s"};
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sc_core::sc_vector<sc_core::sc_signal<bool, sc_core::SC_MANY_WRITERS>> irq_int_s{"irq_int_s", 32}, local_int_s{"local_int_s", 16};
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sc_core::sc_signal<bool, sc_core::SC_MANY_WRITERS> core_int_s{"core_int_s"};
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sc_core::sc_vector<sc_core::sc_signal<bool, sc_core::SC_MANY_WRITERS>> irq_int_s{"irq_int_s", 32};
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sc_core::sc_vector<sc_core::sc_signal<bool, sc_core::SC_MANY_WRITERS>> clint_int_s{"clint_int_s", 16};
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sc_core::sc_signal<uint64_t> mtime_s{"mtime_s"};
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void gen_reset();
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};
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2
vpvper
2
vpvper
Submodule vpvper updated: 6413f14b18...d9c206f61a
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