Mirrors/RISCV-VP
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updates dbt-rise-riscv and vpvper

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This commit is contained in:
Eyck Jentzsch
2025-12-06 21:24:45 +01:00
parent 7e817aa9e3
commit f234849bd1
5 changed files with 10 additions and 14 deletions
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2
dbt-rise-riscv

Submodule dbt-rise-riscv updated: 3678067320...4990d15a35

2
scc

Submodule scc updated: 3f5d963ae0...c54fc1b084

12
src/vp/system.cpp
View File

@@ -5,7 +5,6 @@
*/ */
#include "system.h" #include "system.h"
#include <minres/timer.h> #include <minres/timer.h>
#include <minres/uart.h> #include <minres/uart.h>
#include <scc/utilities.h> #include <scc/utilities.h>
@@ -57,9 +56,9 @@ system::system(sc_core::sc_module_name nm)
aclint.mtime_clk_i(mtime_clk); aclint.mtime_clk_i(mtime_clk);
aclint.mtime_o(mtime_s); aclint.mtime_o(mtime_s);
aclint.mtime_int_o(mtime_int_s); aclint.mtime_int_o[0](clint_int_s[sysc::riscv::TIMER_IRQ]);
aclint.msip_int_o(msip_int_s); aclint.msip_int_o[0](clint_int_s[sysc::riscv::SW_IRQ]);
irq_ctrl.irq_o(core_int_s); irq_ctrl.irq_o(clint_int_s[sysc::riscv::EXT_IRQ]);
irq_ctrl.pending_irq_i(irq_int_s); irq_ctrl.pending_irq_i(irq_int_s);
uart0.irq_o(irq_int_s[0]); uart0.irq_o(irq_int_s[0]);
@@ -68,10 +67,7 @@ system::system(sc_core::sc_module_name nm)
qspi.irq_o(irq_int_s[3]); qspi.irq_o(irq_int_s[3]);
core_complex.mtime_i(mtime_s); core_complex.mtime_i(mtime_s);
core_complex.timer_irq_i(mtime_int_s); core_complex.clint_irq_i(clint_int_s);
core_complex.ext_irq_i(core_int_s);
core_complex.local_irq_i(local_int_s);
core_complex.sw_irq_i(msip_int_s);
gpio0.pins_i(pins_i); gpio0.pins_i(pins_i);
gpio0.pins_o(pins_o); gpio0.pins_o(pins_o);

6
src/vp/system.h
View File

@@ -63,10 +63,10 @@ private:
scc::memory<8_kB, scc::LT> boot_rom{"boot_rom"}; scc::memory<8_kB, scc::LT> boot_rom{"boot_rom"};
sc_core::sc_signal<sc_core::sc_time> mtime_clk{"mtime_clk"}; sc_core::sc_signal<sc_core::sc_time> mtime_clk{"mtime_clk"};
sc_core::sc_signal<bool, sc_core::SC_MANY_WRITERS> rst_s{"rst_s"}, mtime_int_s{"mtime_int_s"}, msip_int_s{"msip_int_s"}; sc_core::sc_signal<bool, sc_core::SC_MANY_WRITERS> rst_s{"rst_s"};
sc_core::sc_vector<sc_core::sc_signal<bool, sc_core::SC_MANY_WRITERS>> irq_int_s{"irq_int_s", 32}, local_int_s{"local_int_s", 16}; sc_core::sc_vector<sc_core::sc_signal<bool, sc_core::SC_MANY_WRITERS>> irq_int_s{"irq_int_s", 32};
sc_core::sc_signal<bool, sc_core::SC_MANY_WRITERS> core_int_s{"core_int_s"}; sc_core::sc_vector<sc_core::sc_signal<bool, sc_core::SC_MANY_WRITERS>> clint_int_s{"clint_int_s", 16};
sc_core::sc_signal<uint64_t> mtime_s{"mtime_s"}; sc_core::sc_signal<uint64_t> mtime_s{"mtime_s"};
void gen_reset(); void gen_reset();
}; };

2
vpvper

Submodule vpvper updated: 6413f14b18...d9c206f61a