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adds 2GB DRAM and changes addr map

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This commit is contained in:
Eyck Jentzsch
2026-02-01 18:37:44 +01:00
parent d47fdc885f
commit f1326e51ff
3 changed files with 9 additions and 7 deletions
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2
scc

Submodule scc updated: 2d5b268615...9fca1a7895

13
src/vp/system.cpp
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@@ -29,7 +29,7 @@ using namespace vpvper::minres;
system::system(sc_core::sc_module_name nm) system::system(sc_core::sc_module_name nm)
: sc_core::sc_module(nm) : sc_core::sc_module(nm)
, NAMED(ahb_router, 5, 2) , NAMED(ahb_router, 6, 2)
, NAMED(apbBridge, PipelinedMemoryBusToApbBridge_map.size(), 1) { , NAMED(apbBridge, PipelinedMemoryBusToApbBridge_map.size(), 1) {
mtime_clk = (1.0 / 32768) * 1_sec; mtime_clk = (1.0 / 32768) * 1_sec;
@@ -39,11 +39,12 @@ system::system(sc_core::sc_module_name nm)
core_complex.mtime_i(mtime_s); core_complex.mtime_i(mtime_s);
core_complex.clint_irq_i(clint_int_s); core_complex.clint_irq_i(clint_int_s);
ahb_router.bind_target(mem_ram.target, 1, 0x00000000, 128_kB); ahb_router.bind_target(mem_dram.target, 0, 0x00000000, mem_dram.getSize());
ahb_router.bind_target(apbBridge.target[0], 2, 0x10000000, 128_MB); ahb_router.bind_target(mem_ram.target, 1, 0xE0000000, mem_ram.getSize());
ahb_router.bind_target(eth0.socket, 3, 0x18000000, 4_KiB); ahb_router.bind_target(apbBridge.target[0], 2, 0xF0000000, 16_MB);
ahb_router.bind_target(eth1.socket, 4, 0x18001000, 4_KiB); ahb_router.bind_target(eth0.socket, 3, 0xF1000000, 4_KiB);
ahb_router.bind_target(qspi.xip_sck, 0, 0x20000000, 16_MB); ahb_router.bind_target(eth1.socket, 4, 0xF1001000, 4_KiB);
ahb_router.bind_target(qspi.xip_sck, 5, 0xF2000000, 16_MB);
size_t i = 0; size_t i = 0;
for(const auto& e : PipelinedMemoryBusToApbBridge_map) { for(const auto& e : PipelinedMemoryBusToApbBridge_map) {
apbBridge.initiator.at(i)(e.target); apbBridge.initiator.at(i)(e.target);

1
src/vp/system.h
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@@ -66,6 +66,7 @@ private:
vpvper::minres::ethmac_tl eth1{"eth1"}; vpvper::minres::ethmac_tl eth1{"eth1"};
scc::memory<128_kB, scc::LT> mem_ram{"mem_ram"}; scc::memory<128_kB, scc::LT> mem_ram{"mem_ram"};
scc::memory<2_GB, scc::LT> mem_dram{"mem_dram"};
scc::memory<8_kB, scc::LT> boot_rom{"boot_rom"}; scc::memory<8_kB, scc::LT> boot_rom{"boot_rom"};
sc_core::sc_signal<sc_core::sc_time> mtime_clk{"mtime_clk"}; sc_core::sc_signal<sc_core::sc_time> mtime_clk{"mtime_clk"};