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https://github.com/Minres/RISCV-VP.git
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repöace defines with enum
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@@ -17,18 +17,20 @@ namespace vp {
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using namespace sc_core;
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using namespace sc_core;
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using namespace vpvper::minres;
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using namespace vpvper::minres;
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#define UART0_IRQ 16
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enum {
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#define TIMER0_IRQ0 17
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UART0_IRQ = 16,
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#define TIMER0_IRQ1 18
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TIMER0_IRQ0 = 17,
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#define QSPI_IRQ 19
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TIMER0_IRQ1 = 18,
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#define I2S_IRQ 20
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QSPI_IRQ = 19,
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#define CAM_IRQ 21
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I2S_IRQ = 20,
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#define DMA_IRQ 22
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CAM_IRQ = 21,
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#define GPIO_ORQ 23
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DMA_IRQ = 22,
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#define ETH0_IRQ 24
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GPIO_ORQ = 23,
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#define ETH1_IRQ 25
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ETH0_IRQ = 24,
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#define MDIO0_IRQ 26
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ETH1_IRQ = 25,
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#define MDIO1_IRQ 27
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MDIO0_IRQ = 26,
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MDIO1_IRQ = 27
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};
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system::system(sc_core::sc_module_name nm)
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system::system(sc_core::sc_module_name nm)
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: sc_core::sc_module(nm)
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: sc_core::sc_module(nm)
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