Mirrors/RISCV-VP
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updates submodules

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This commit is contained in:
eyck
2026-08-12 09:38:21 +02:00
parent ad5ddf05db
commit de469f8b38
5 changed files with 5 additions and 5 deletions
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dbt-rise-core
+1 -1
Submodule dbt-rise-core updated: fa86b08981...29e97c021c
dbt-rise-riscv
+1 -1
Submodule dbt-rise-riscv updated: 64967f772c...e7745dae8e
scc
+1 -1
Submodule scc updated: 9a76798134...557b856dd2
src/vp/system.cpp
+1 -1
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@@ -129,7 +129,7 @@ void system::start_of_simulation() {
gp.set_command(tlm::TLM_IGNORE_COMMAND); gp.set_command(tlm::TLM_IGNORE_COMMAND);
gp.set_data_length(trace_buffer.size()); gp.set_data_length(trace_buffer.size());
gp.set_streaming_width(trace_buffer.size()); gp.set_streaming_width(trace_buffer.size());
scc::host_mem_map_extension ext{trace_buffer.data()}; scc::host_mem_map_extension ext{trace_buffer.data(), trace_buffer.size()};
gp.set_extension(&ext); gp.set_extension(&ext);
mem_trace.target.get_base_interface().transport_dbg(gp); mem_trace.target.get_base_interface().transport_dbg(gp);
gp.set_extension<scc::host_mem_map_extension>(nullptr); gp.set_extension<scc::host_mem_map_extension>(nullptr);
src/vp/system.h
+1 -1
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@@ -56,7 +56,7 @@ public:
system(sc_core::sc_module_name nm); system(sc_core::sc_module_name nm);
private: private:
#include "../vp/gen/PipelinedMemoryBusToApbBridge.h" // IWYU pragma: keep #include "gen/PipelinedMemoryBusToApbBridge.h" // IWYU pragma: keep
sysc::riscv::core_complex<> core_complex{"core_complex"}; sysc::riscv::core_complex<> core_complex{"core_complex"};
scc::router<> main_bus, peripheral_bus; scc::router<> main_bus, peripheral_bus;
vpvper::minres::gpio_tl gpio0{"gpio0"}; vpvper::minres::gpio_tl gpio0{"gpio0"};