mirror of
https://github.com/Minres/RISCV-VP.git
synced 2025-12-17 08:51:35 +00:00
fixes dgb access for 64bit cores
This commit is contained in:
18
.vscode/launch.json
vendored
18
.vscode/launch.json
vendored
@@ -17,6 +17,7 @@
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},
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},
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"cwd": "${workspaceRoot}",
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"cwd": "${workspaceRoot}",
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"gdb": "riscv64-unknown-elf-gdb",
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"gdb": "riscv64-unknown-elf-gdb",
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"openGdbConsole": true,
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"presentation": {
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"presentation": {
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"hidden": false,
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"hidden": false,
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"group": "FW Debug",
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"group": "FW Debug",
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@@ -30,11 +31,16 @@
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"cwd": "${workspaceRoot}",
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"cwd": "${workspaceRoot}",
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"program": "${workspaceFolder}/build/Debug/src/riscv-vp",
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"program": "${workspaceFolder}/build/Debug/src/riscv-vp",
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"arguments": "--isa 'rv32gc|msu_vp' -v DEBUG --disass -f fw/hello-world/hello.elf -g 10000",
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"arguments": "--isa 'rv32gc|msu_vp' -v DEBUG --disass -f fw/hello-world/hello.elf -g 10000",
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"presentation": {
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"openGdbConsole": true
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"hidden": false,
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},
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"group": "FW Debug",
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{
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"order": 1
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"type": "gdb",
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}
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"request": "launch",
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"name": "Launch 64bit VP with gdbserver",
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"cwd": "${workspaceRoot}",
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"program": "${workspaceFolder}/build/Debug/src/riscv-vp",
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"arguments": "--isa 'rv64gc|msu_vp' -v TRACEALL --disass -f fw/hello-world/hello.elf -g 10000",
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"openGdbConsole": true
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},
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},
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{
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{
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"type": "gdb",
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"type": "gdb",
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@@ -42,7 +48,7 @@
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"name": "Launch VP",
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"name": "Launch VP",
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"cwd": "${workspaceRoot}",
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"cwd": "${workspaceRoot}",
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"program": "${workspaceFolder}/build/Debug/src/riscv-vp",
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"program": "${workspaceFolder}/build/Debug/src/riscv-vp",
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"arguments": "-v DEBUG -t 3 --isa tgc5c -f fw/hello-world/hello.elf",
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"arguments": "-v DEBUG -t 3 --isa 'tgc5c|mu_p' -f fw/hello-world/hello.elf",
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"openGdbConsole": true
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"openGdbConsole": true
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},
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},
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{
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{
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Submodule dbt-rise-riscv updated: f4bfd06d7e...48f8983d7e
@@ -8,6 +8,8 @@ BOARD=riscv_vp
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LINK_TARGET=flash
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LINK_TARGET=flash
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RISCV_ARCH:=rv32imc
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RISCV_ARCH:=rv32imc
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RISCV_ABI:=ilp32
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RISCV_ABI:=ilp32
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#RISCV_ARCH:=rv64imc
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#RISCV_ABI:=lp64
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LDFLAGS := -g -march=$(RISCV_ARCH) -mabi=$(RISCV_ABI)
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LDFLAGS := -g -march=$(RISCV_ARCH) -mabi=$(RISCV_ABI)
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compiler := $(shell which riscv64-unknown-elf-gcc)
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compiler := $(shell which riscv64-unknown-elf-gcc)
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