mirror of
https://github.com/Minres/RISCV-VP.git
synced 2025-12-17 17:01:35 +00:00
updates dbt-rise-tgc to feature/updated_implementation
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@@ -76,10 +76,11 @@ int sc_main(int argc, char* argv[]) {
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auto tx_trace_type =
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static_cast<scc::tracer::file_type>(trace_level >> 1); // bit3-bit1 define the kind of transaction trace
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auto trace_default_on = parser.is_set("trace-default-on");
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cfg.set_value("$$$scc_tracer$$$.tx_trace_type", static_cast<unsigned>(scc::tracer::file_type::FTR));
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cfg.set_value("$$$scc_tracer$$$.sig_trace_type", static_cast<unsigned>(scc::tracer::file_type::SC_VCD));
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tracer =
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scc::make_unique<scc::configurable_tracer>(file_name, tx_trace_type, enable_sig_trace, trace_default_on);
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if(parser.is_set("trace-default-off"))
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cfg.set_value("scc_tracer.default_trace_enable", false);
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cfg.set_value("scc_tracer.tx_trace_type", static_cast<unsigned>(scc::tracer::file_type::FTR));
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cfg.set_value("scc_tracer.sig_trace_type", static_cast<unsigned>(scc::tracer::file_type::FST));
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tracer = scc::make_unique<scc::configurable_tracer>(file_name, tx_trace_type, enable_sig_trace);
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}
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///////////////////////////////////////////////////////////////////////////
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// instantiate top level
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@@ -77,10 +77,7 @@ system::system(sc_core::sc_module_name nm)
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timer0.clear_i(t0_clear_i);
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timer0.tick_i(t0_tick_i);
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qspi.ssclk_o(ssclk_o);
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qspi.dq_o(dq_o);
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qspi.dq_i(dq_i);
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qspi.oe_o(dq_oe_o);
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qspi.spi_i(mspi0);
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SC_METHOD(gen_reset);
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sensitive << erst_n;
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@@ -9,9 +9,7 @@
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#include "minres/irq.h"
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#include "minres/timer.h"
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#include <array>
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#include <cci_configuration>
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#include <memory>
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#include <minres/aclint.h>
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#include <minres/gpio.h>
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#include <minres/qspi.h>
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@@ -40,10 +38,7 @@ public:
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sc_core::sc_in<bool> uart0_rx_i{"uart0_rx_i"};
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sc_core::sc_vector<sc_core::sc_in<bool>> t0_clear_i{"t0_clear_i", vpvper::minres::timer::CLEAR_CNT};
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sc_core::sc_vector<sc_core::sc_in<bool>> t0_tick_i{"t0_tick_i", vpvper::minres::timer::TICK_CNT - 1};
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sc_core::sc_out<bool> ssclk_o{"ssclk_o"};
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sc_core::sc_vector<sc_core::sc_out<bool>> dq_o{"dq_o", 4};
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sc_core::sc_vector<sc_core::sc_out<bool>> dq_oe_o{"dq_oe_o", 4};
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sc_core::sc_vector<sc_core::sc_in<bool>> dq_i{"dq_i", 4};
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spi::spi_pkt_initiator_socket<> mspi0{"mspi0"};
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sc_core::sc_in<sc_core::sc_time> clk_i{"clk_i"};
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@@ -21,10 +21,8 @@ tb::tb(const sc_core::sc_module_name& nm)
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top.uart0_tx_o(uart0_tx_o);
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top.t0_clear_i(t0_clear_i);
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top.t0_tick_i(t0_tick_i);
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top.ssclk_o(ssclk_o);
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top.dq_o(dq_o);
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top.dq_i(dq_i);
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top.dq_oe_o(dq_oe_o);
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top.mspi0(spi());
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spi(0)(qspi_mem.spi_t);
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top.clk_i(clk_i);
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clk_i = 10_ns;
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}
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11
src/vp/tb.h
11
src/vp/tb.h
@@ -7,11 +7,12 @@
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#ifndef SRC_VP_TB_H_
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#define SRC_VP_TB_H_
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#include <generic/spi_mem.h>
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#include <generic/terminal.h>
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#include <systemc>
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#include "../vp/rst_gen.h"
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#include "../vp/system.h"
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#include "rst_gen.h"
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#include "system.h"
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namespace tgc_vp {
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class tb : public sc_core::sc_module {
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@@ -27,10 +28,8 @@ public:
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sc_core::sc_signal<bool> uart0_rx_i{"uart0_rx_i"};
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sc_core::sc_vector<sc_core::sc_signal<bool>> t0_clear_i{"t0_clear_i", vpvper::minres::timer::CLEAR_CNT};
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sc_core::sc_vector<sc_core::sc_signal<bool>> t0_tick_i{"t0_tick_i", vpvper::minres::timer::TICK_CNT - 1};
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sc_core::sc_signal<bool> ssclk_o{"ssclk_o"};
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sc_core::sc_vector<sc_core::sc_signal<bool>> dq_o{"dq_o", 4};
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sc_core::sc_vector<sc_core::sc_signal<bool>> dq_oe_o{"dq_oe_o", 4};
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sc_core::sc_vector<sc_core::sc_signal<bool>> dq_i{"dq_i", 4};
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spi::spi_channel spi{"spi", 1};
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vpvper::generic::spi_mem qspi_mem{"qspi_mem"};
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sc_core::sc_signal<sc_core::sc_time> clk_i{"clk_i"};
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};
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