Mirrors/RISCV-VP
6
0
Fork 3
mirror of https://github.com/Minres/RISCV-VP.git synced 2026-04-14 19:21:37 +01:00
Code Issues Packages Projects Releases Wiki Activity

initial version

Browse Source
This commit is contained in:
Eyck Jentzsch
2024-06-30 17:47:05 +02:00
commit 15144ca608
54 changed files with 2512 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

21
src/vp/gen/PipelinedMemoryBusToApbBridge.h Normal file
View File

@@ -0,0 +1,21 @@
/*
* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
*
* SPDX-License-Identifier: Apache-2.0
*
* Generated at 2024-02-08 14:41:56 UTC
* by peakrdl_mnrs version 1.2.2
*/
#pragma once
// need double braces, see https://stackoverflow.com/questions/6893700/how-to-construct-stdarray-object-with-initializer-list#6894191
const std::array<scc::target_memory_map_entry<scc::LT>, 6> PipelinedMemoryBusToApbBridge_map = {{
{ gpio0.socket, 0x0, 0xc },
{ uart0.socket, 0x1000, 0x14 },
{ timer0.socket, 0x20000, 0x1c },
{ aclint.socket, 0x30000, 0xc000 },
{ irq_ctrl.socket, 0x40000, 0x8 },
{ qspi.socket, 0x50000, 0x5c },
//{ bootloader.socket, 0x80000, 0x400 },
}} ;

26
src/vp/gen/platform_mmap.h Normal file
View File

@@ -0,0 +1,26 @@
/*
* Copyright (c) 2019 -2021 MINRES Technolgies GmbH
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _PLATFORM_MMAP_H_
#define _PLATFORM_MMAP_H_
// need double braces, see
// https://stackoverflow.com/questions/6893700/how-to-construct-stdarray-object-with-initializer-list#6894191
const std::array<scc::target_memory_map_entry<scc::LT>, 13> platfrom_mmap = {{
{clint.socket, 0x2000000, 0xc000},
{plic.socket, 0xc000000, 0x200008},
{aon.socket, 0x10000000, 0x150},
{prci.socket, 0x10008000, 0x14},
{gpio0.socket, 0x10012000, 0x44},
{uart0.socket, 0x10013000, 0x1c},
{qspi0.socket, 0x10014000, 0x78},
{pwm0.socket, 0x10015000, 0x30},
{uart1.socket, 0x10023000, 0x1c},
{qspi1.socket, 0x10024000, 0x78},
{pwm1.socket, 0x10025000, 0x30},
{qspi2.socket, 0x10034000, 0x78},
{pwm2.socket, 0x10035000, 0x30},
}};
#endif /* _PLATFORM_MMAP_H_ */

25
src/vp/platform.rdl Normal file
View File

@@ -0,0 +1,25 @@
`include "gpio.rdl"
`include "uart.rdl"
`include "spi.rdl"
`include "pwm.rdl"
`include "plic.rdl"
`include "aon.rdl"
`include "prci.rdl"
`include "clint.rdl"
addrmap e300_plat_t {
lsb0;
clint_regs clint @0x02000000;
plic_regs plic @0x0C000000;
aon_regs aon @0x10000000;
prci_regs prci @0x10008000;
gpio_regs gpio0 @0x10012000;
uart_regs uart0 @0x10013000;
spi_regs qspi0 @0x10014000;
pwm_regs pwm0 @0x10015000;
uart_regs uart1 @0x10023000;
spi_regs qspi1 @0x10024000;
pwm_regs pwm1 @0x10025000;
spi_regs qspi2 @0x10034000;
pwm_regs pwm2 @0x10035000;
} e300_plat;

27
src/vp/rst_gen.h Normal file
View File

@@ -0,0 +1,27 @@
/*
* Copyright (c) 2019 -2021 MINRES Technolgies GmbH
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <systemc>
namespace tgc_vp {
class rst_gen : public sc_core::sc_module {
SC_HAS_PROCESS(rst_gen);
public:
rst_gen(sc_core::sc_module_name const& nm) {
SC_THREAD(run);
}
sc_core::sc_out<bool> rst_n{"rst_n"};
private:
void run(){
rst_n.write(false);
wait(100_ns);
rst_n.write(true);
}
};
} /* namespace tgc_vp */

96
src/vp/system.cpp Normal file
View File

@@ -0,0 +1,96 @@
/*
* Copyright (c) 2019 -2021 MINRES Technolgies GmbH
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "../vp/system.h"
#include "minres/timer.h"
#include "minres/uart.h"
#include "scc/utilities.h"
namespace tgc_vp {
using namespace sc_core;
using namespace vpvper::minres;
using namespace sysc::tgfs;
system::system(sc_core::sc_module_name nm)
: sc_core::sc_module(nm)
, NAMED(ahb_router, 3, 2)
, NAMED(apbBridge, PipelinedMemoryBusToApbBridge_map.size(), 1){
core_complex.ibus(ahb_router.target[0]);
core_complex.dbus(ahb_router.target[1]);
ahb_router.initiator.at(0)(qspi.xip_sck);
ahb_router.set_target_range(0, 0xE0000000, 16_MB);
ahb_router.initiator.at(1)(mem_ram.target);
ahb_router.set_target_range(1, 0x80000000, 32_kB);
ahb_router.initiator.at(2)(apbBridge.target[0]);
ahb_router.set_target_range(2, 0xF0000000, 256_MB);
size_t i = 0;
for (const auto &e : PipelinedMemoryBusToApbBridge_map) {
apbBridge.initiator.at(i)(e.target);
apbBridge.set_target_range(i, e.start, e.size);
i++;
}
gpio0.clk_i(clk_i);
uart0.clk_i(clk_i);
timer0.clk_i(clk_i);
aclint.clk_i(clk_i);
irq_ctrl.clk_i(clk_i);
qspi.clk_i(clk_i);
core_complex.clk_i(clk_i);
//mem_ram.clk_i(clk_i);
gpio0.rst_i(rst_s);
uart0.rst_i(rst_s);
timer0.rst_i(rst_s);
aclint.rst_i(rst_s);
irq_ctrl.rst_i(rst_s);
qspi.rst_i(rst_s);
core_complex.rst_i(rst_s);
aclint.mtime_int_o(mtime_int_s);
aclint.msip_int_o(msip_int_s);
irq_ctrl.irq_o(core_int_s);
irq_ctrl.pending_irq_i(irq_int_s);
uart0.irq_o(irq_int_s[0]);
timer0.interrupt_o[0](irq_int_s[1]);
timer0.interrupt_o[1](irq_int_s[2]);
qspi.irq_o(irq_int_s[3]);
core_complex.timer_irq_i(mtime_int_s);
core_complex.ext_irq_i(core_int_s);
core_complex.local_irq_i(local_int_s);
core_complex.sw_irq_i(msip_int_s);
gpio0.pins_i(pins_i);
gpio0.pins_o(pins_o);
gpio0.oe_o(pins_oe_o);
uart0.tx_o(uart0_tx_o);
uart0.rx_i(uart0_rx_i);
timer0.clear_i(t0_clear_i);
timer0.tick_i(t0_tick_i);
qspi.ssclk_o(ssclk_o);
qspi.dq_o(dq_o);
qspi.dq_i(dq_i);
qspi.oe_o(dq_oe_o);
SC_METHOD(gen_reset);
sensitive << erst_n;
}
void system::gen_reset(){
if(erst_n.read())
rst_s = 0;
else rst_s = 1;
}
} /* namespace sysc */

78
src/vp/system.h Normal file
View File

@@ -0,0 +1,78 @@
/*
* Copyright (c) 2019 -2021 MINRES Technolgies GmbH
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _PLATFORM_H_
#define _PLATFORM_H_
#include "minres/irq.h"
#include "minres/timer.h"
#include <minres/aclint.h>
#include <minres/gpio.h>
#include <minres/qspi.h>
#include <sysc/communication/sc_clock.h>
#include <sysc/communication/sc_signal_ports.h>
#include <sysc/core_complex.h>
#include <minres/uart.h>
#include <cci_configuration>
#include <scc/memory.h>
#include <scc/router.h>
#include <scc/utilities.h>
#include <sysc/kernel/sc_time.h>
#include <sysc/utils/sc_vector.h>
#include <tlm/scc/tlm_signal_sockets.h>
#include <array>
#include <memory>
#include <sysc/kernel/sc_module.h>
namespace tgc_vp {
class system : public sc_core::sc_module {
public:
SC_HAS_PROCESS(system);// NOLINT
sc_core::sc_vector<sc_core::sc_out<bool>> pins_o{"pins_o",32};
sc_core::sc_vector<sc_core::sc_out<bool>> pins_oe_o{"pins_oe_o", 32};
sc_core::sc_vector<sc_core::sc_in<bool>> pins_i{"pins_i", 32};
sc_core::sc_out<bool> uart0_tx_o {"uart0_tx_o"};
sc_core::sc_in<bool> uart0_rx_i {"uart0_rx_i"};
sc_core::sc_vector<sc_core::sc_in<bool>> t0_clear_i {"t0_clear_i", vpvper::minres::timer::CLEAR_CNT};
sc_core::sc_vector<sc_core::sc_in<bool>> t0_tick_i {"t0_tick_i", vpvper::minres::timer::TICK_CNT-1};
sc_core::sc_out<bool> ssclk_o{"ssclk_o"};
sc_core::sc_vector<sc_core::sc_out<bool>> dq_o{"dq_o", 4};
sc_core::sc_vector<sc_core::sc_out<bool>> dq_oe_o{"dq_oe_o", 4};
sc_core::sc_vector<sc_core::sc_in<bool>> dq_i{"dq_i", 4};
sc_core::sc_in<sc_core::sc_time> clk_i{"clk_i"};
sc_core::sc_in<bool> erst_n{"erst_n"};
system(sc_core::sc_module_name nm);
private:
sysc::tgfs::core_complex core_complex{"core_complex"};
scc::router<> ahb_router, apbBridge;
vpvper::minres::gpio_tl gpio0{"gpio0"};
vpvper::minres::uart_tl uart0{"uart0"};
vpvper::minres::timer_tl timer0{"timer0"};
vpvper::minres::aclint_tl aclint{"aclint"};
vpvper::minres::irq_tl irq_ctrl{"irq_ctrl"};
vpvper::minres::qspi_tl qspi{"qspi"};
//scc::memory<1_kB, scc::LT> bootloader{"bootloader"};
scc::memory<32_kB, scc::LT> mem_ram {"mem_ram"};
sc_core::sc_signal<bool, sc_core::SC_MANY_WRITERS> rst_s{"rst_s"}, mtime_int_s{"mtime_int_s"}, msip_int_s{"msip_int_s"};
sc_core::sc_vector<sc_core::sc_signal<bool, sc_core::SC_MANY_WRITERS>> irq_int_s{"irq_int_s", 32}, local_int_s{"local_int_s", 16};
sc_core::sc_signal<bool, sc_core::SC_MANY_WRITERS> core_int_s{"core_int_s"};
void gen_reset();
#include "../vp/gen/PipelinedMemoryBusToApbBridge.h"
};
} /* namespace sysc */
#endif /* _PLATFORM_H_ */

30
src/vp/tb.cpp Normal file
View File

@@ -0,0 +1,30 @@
/*
* Copyright (c) 2019 -2021 MINRES Technolgies GmbH
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "../vp/tb.h"
#include <sysc/kernel/sc_time.h>
namespace tgc_vp {
SC_HAS_PROCESS(tb);
tb::tb(const sc_core::sc_module_name &nm): sc_core::sc_module(nm) {
top.erst_n(rst_n);
rst_gen.rst_n(rst_n);
top.pins_o(pins_o);
top.pins_i(pins_i);
top.pins_oe_o(pins_oe_o);
top.uart0_rx_i(uart0_rx_i);
top.uart0_tx_o(uart0_tx_o);
top.t0_clear_i(t0_clear_i);
top.t0_tick_i(t0_tick_i);
top.ssclk_o(ssclk_o);
top.dq_o(dq_o);
top.dq_i(dq_i);
top.dq_oe_o(dq_oe_o);
top.clk_i(clk_i);
clk_i = 10_ns;
}
}

39
src/vp/tb.h Normal file
View File

@@ -0,0 +1,39 @@
/*
* Copyright (c) 2019 -2021 MINRES Technolgies GmbH
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef SRC_VP_TB_H_
#define SRC_VP_TB_H_
#include <generic/terminal.h>
#include <systemc>
#include "../vp/rst_gen.h"
#include "../vp/system.h"
namespace tgc_vp {
class tb : public sc_core::sc_module {
public:
tb(sc_core::sc_module_name const& nm);
tgc_vp::system top{"top"};
tgc_vp::rst_gen rst_gen{"rst_gen"};
sc_core::sc_signal<bool> rst_n{"rst_n"};
sc_core::sc_vector<sc_core::sc_signal<bool>> pins_o{"pins_o",32};
sc_core::sc_vector<sc_core::sc_signal<bool>> pins_oe_o{"pins_oe_o", 32};
sc_core::sc_vector<sc_core::sc_signal<bool>> pins_i{"pins_i", 32};
sc_core::sc_signal<bool> uart0_tx_o {"uart0_tx_o"};
sc_core::sc_signal<bool> uart0_rx_i {"uart0_rx_i"};
sc_core::sc_vector<sc_core::sc_signal<bool>> t0_clear_i {"t0_clear_i", vpvper::minres::timer::CLEAR_CNT};
sc_core::sc_vector<sc_core::sc_signal<bool>> t0_tick_i {"t0_tick_i", vpvper::minres::timer::TICK_CNT-1};
sc_core::sc_signal<bool> ssclk_o{"ssclk_o"};
sc_core::sc_vector<sc_core::sc_signal<bool>> dq_o{"dq_o", 4};
sc_core::sc_vector<sc_core::sc_signal<bool>> dq_oe_o{"dq_oe_o", 4};
sc_core::sc_vector<sc_core::sc_signal<bool>> dq_i{"dq_i", 4};
sc_core::sc_signal<sc_core::sc_time> clk_i{"clk_i"};
};
} /* namespace tgc_vp */
#endif /* SRC_VP_TB_H_ */