Mirrors/RISCV-VP
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updates submodules and sc_main to match them

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This commit is contained in:
Eyck Jentzsch
2025-11-27 17:57:30 +01:00
parent 1bbcbc9a69
commit 1338cbffb9
11 changed files with 33 additions and 27 deletions
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7
src/vp/system.h
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@@ -7,6 +7,7 @@
#ifndef SRC_VP_SYSTEM_H_
#define SRC_VP_SYSTEM_H_
#include "tlm/scc/quantum_keeper.h"
#include <cci_configuration>
#include <minres/aclint.h>
#include <minres/gpio.h>
@@ -20,7 +21,7 @@
#include <sysc/communication/sc_clock.h>
#include <sysc/communication/sc_signal.h>
#include <sysc/communication/sc_signal_ports.h>
#include <sysc/core_complex_mt.h>
#include <sysc/core_complex.h>
#include <sysc/kernel/sc_module.h>
#include <sysc/kernel/sc_time.h>
#include <sysc/utils/sc_vector.h>
@@ -48,7 +49,8 @@ public:
system(sc_core::sc_module_name nm);
private:
sysc::riscv::core_complex_mt<> core_complex{"core_complex"};
#include "../vp/gen/PipelinedMemoryBusToApbBridge.h" // IWYU pragma: keep
sysc::riscv::core_complex<scc::LT, tlm::scc::quantumkeeper_mt> core_complex{"core_complex"};
scc::router<> ahb_router, apbBridge;
vpvper::minres::gpio_tl gpio0{"gpio0"};
vpvper::minres::uart_tl uart0{"uart0"};
@@ -67,7 +69,6 @@ private:
sc_core::sc_signal<bool, sc_core::SC_MANY_WRITERS> core_int_s{"core_int_s"};
sc_core::sc_signal<uint64_t> mtime_s{"mtime_s"};
void gen_reset();
#include "../vp/gen/PipelinedMemoryBusToApbBridge.h" // IWYU pragma: keep
};
} // namespace vp