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updates dbt-rise-riscv and makes system::clint_int_s dependend on the size of the core clint_irq_i

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This commit is contained in:
Eyck Jentzsch
2026-01-29 20:59:33 +01:00
parent c03d6e969c
commit 09083643bc
3 changed files with 12 additions and 12 deletions
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2
dbt-rise-riscv

Submodule dbt-rise-riscv updated: de97a24567...2984a43885

20
src/vp/system.cpp
View File

@@ -33,8 +33,11 @@ system::system(sc_core::sc_module_name nm)
, NAMED(apbBridge, PipelinedMemoryBusToApbBridge_map.size(), 1) { , NAMED(apbBridge, PipelinedMemoryBusToApbBridge_map.size(), 1) {
mtime_clk = (1.0 / 32768) * 1_sec; mtime_clk = (1.0 / 32768) * 1_sec;
clint_int_s.init(core_complex.clint_irq_i.size());
core_complex.ibus(ahb_router.target[0]); core_complex.ibus(ahb_router.target[0]);
core_complex.dbus(ahb_router.target[1]); core_complex.dbus(ahb_router.target[1]);
core_complex.mtime_i(mtime_s);
core_complex.clint_irq_i(clint_int_s);
ahb_router.bind_target(mem_ram.target, 1, 0x00000000, 128_kB); ahb_router.bind_target(mem_ram.target, 1, 0x00000000, 128_kB);
ahb_router.bind_target(apbBridge.target[0], 2, 0x10000000, 128_MB); ahb_router.bind_target(apbBridge.target[0], 2, 0x10000000, 128_MB);
@@ -48,22 +51,21 @@ system::system(sc_core::sc_module_name nm)
i++; i++;
} }
core_complex.clk_i(clk_i);
gpio0.clk_i(clk_i); gpio0.clk_i(clk_i);
uart0.clk_i(clk_i); uart0.clk_i(clk_i);
timer0.clk_i(clk_i); timer0.clk_i(clk_i);
aclint.clk_i(clk_i); aclint.clk_i(clk_i);
qspi.clk_i(clk_i); qspi.clk_i(clk_i);
core_complex.clk_i(clk_i);
// mem_ram.clk_i(clk_i);
eth0.clk_i(clk_i); eth0.clk_i(clk_i);
eth1.clk_i(clk_i); eth1.clk_i(clk_i);
core_complex.rst_i(rst_s);
gpio0.rst_i(rst_s); gpio0.rst_i(rst_s);
uart0.rst_i(rst_s); uart0.rst_i(rst_s);
timer0.rst_i(rst_s); timer0.rst_i(rst_s);
aclint.rst_i(rst_s); aclint.rst_i(rst_s);
qspi.rst_i(rst_s); qspi.rst_i(rst_s);
core_complex.rst_i(rst_s);
eth0.rst_i(rst_s); eth0.rst_i(rst_s);
eth1.rst_i(rst_s); eth1.rst_i(rst_s);
@@ -76,18 +78,11 @@ system::system(sc_core::sc_module_name nm)
timer0.interrupt_o[0](clint_int_s[TIMER0_IRQ0]); timer0.interrupt_o[0](clint_int_s[TIMER0_IRQ0]);
timer0.interrupt_o[1](clint_int_s[TIMER0_IRQ1]); timer0.interrupt_o[1](clint_int_s[TIMER0_IRQ1]);
qspi.irq_o(clint_int_s[QSPI_IRQ]); qspi.irq_o(clint_int_s[QSPI_IRQ]);
eth0.eth_tx(eth0_tx);
eth0_rx(eth0.eth_rx);
eth1.eth_tx(eth1_tx);
eth1_rx(eth1.eth_rx);
eth0.irq_o[0](clint_int_s[ETH0_IRQ]); eth0.irq_o[0](clint_int_s[ETH0_IRQ]);
eth1.irq_o[0](clint_int_s[ETH1_IRQ]); eth1.irq_o[0](clint_int_s[ETH1_IRQ]);
eth0.irq_o[1](clint_int_s[MDIO0_IRQ]); eth0.irq_o[1](clint_int_s[MDIO0_IRQ]);
eth1.irq_o[1](clint_int_s[MDIO1_IRQ]); eth1.irq_o[1](clint_int_s[MDIO1_IRQ]);
core_complex.mtime_i(mtime_s);
core_complex.clint_irq_i(clint_int_s);
gpio0.pins_i(pins_i); gpio0.pins_i(pins_i);
gpio0.pins_o(pins_o); gpio0.pins_o(pins_o);
gpio0.oe_o(pins_oe_o); gpio0.oe_o(pins_oe_o);
@@ -100,6 +95,11 @@ system::system(sc_core::sc_module_name nm)
qspi.spi_i(mspi0); qspi.spi_i(mspi0);
eth0.eth_tx(eth0_tx);
eth0_rx(eth0.eth_rx);
eth1.eth_tx(eth1_tx);
eth1_rx(eth1.eth_rx);
SC_METHOD(gen_reset); SC_METHOD(gen_reset);
sensitive << erst_n; sensitive << erst_n;
} }

2
src/vp/system.h
View File

@@ -71,7 +71,7 @@ private:
sc_core::sc_signal<sc_core::sc_time> mtime_clk{"mtime_clk"}; sc_core::sc_signal<sc_core::sc_time> mtime_clk{"mtime_clk"};
sc_core::sc_signal<bool, sc_core::SC_MANY_WRITERS> rst_s{"rst_s"}; sc_core::sc_signal<bool, sc_core::SC_MANY_WRITERS> rst_s{"rst_s"};
sc_core::sc_vector<sc_core::sc_signal<bool, sc_core::SC_MANY_WRITERS>> clint_int_s{"clint_int_s", 32}; sc_core::sc_vector<sc_core::sc_signal<bool, sc_core::SC_MANY_WRITERS>> clint_int_s{"clint_int_s", 0};
sc_core::sc_signal<uint64_t> mtime_s{"mtime_s"}; sc_core::sc_signal<uint64_t> mtime_s{"mtime_s"};
void gen_reset(); void gen_reset();
}; };