Xiang W fc82e84329 lib: sbi: Fix is_region_valid() ...

When order is equal to __riscv_xlen, the shift operation will not perform
any operation, which will cause reg->base & (BIT(reg->order) - 1) to always
be 0, and the condition has not been established.

This patch fixes this bug.

Signed-off-by: Xiang W <wxjstz@126.com>
Reviewed-by: Anup Patel <anup@brainfault.org>

2022-12-04 21:52:52 +05:30

..

sbi

lib: sbi: Fix is_region_valid()

2022-12-04 21:52:52 +05:30

utils

lib: utils/serial: Fix semihosting compile error using LLVM

2022-11-15 16:38:41 +05:30