forked from Mirrors/opensbi

The example should use watchdog as nodename instead of wdt. This is defined in watchdog common schemas: https://github.com/torvalds/linux/blob/v6.0/Documentation/devicetree/bindings/watchdog/watchdog.yaml#L19 Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Anup Patel <anup@brainfault.org>
208 lines
5.6 KiB
Markdown
208 lines
5.6 KiB
Markdown
Andes AE350 SoC Platform
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========================
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The AE350 AXI/AHB-based platform N25(F)/NX25(F)/D25F/A25/AX25 CPU with level-one
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memories, interrupt controller, debug module, AXI and AHB Bus Matrix Controller,
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AXI-to-AHB Bridge and a collection of fundamental AHB/APB bus IP components
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pre-integrated together as a system design. The high-quality and configurable
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AHB/APB IPs suites a majority embedded systems, and the verified platform serves
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as a starting point to jump start SoC designs.
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To build platform specific library and firmwares, provide the
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*PLATFORM=generic* parameter to the top level `make` command.
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Platform Options
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----------------
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The Andes AE350 platform does not have any platform-specific options.
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Building Andes AE350 Platform
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-----------------------------
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AE350's dts is included in https://github.com/andestech/linux/tree/RISCV-Linux-5.4-ast-v5_1_0-branch
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**Linux Kernel Payload**
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```
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make PLATFORM=generic FW_PAYLOAD_PATH=<linux_build_directory>/arch/riscv/boot/Image FW_FDT_PATH=<ae350.dtb path>
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```
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DTS Example: (Quad-core AX45MP)
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-------------------------------
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```
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compatible = "andestech,ae350";
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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timebase-frequency = <60000000>;
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CPU0: cpu@0 {
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device_type = "cpu";
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reg = <0>;
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status = "okay";
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compatible = "riscv";
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riscv,isa = "rv64imafdc";
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riscv,priv-major = <1>;
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riscv,priv-minor = <10>;
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mmu-type = "riscv,sv48";
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clock-frequency = <60000000>;
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i-cache-size = <0x8000>;
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i-cache-sets = <256>;
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i-cache-line-size = <64>;
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i-cache-block-size = <64>;
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d-cache-size = <0x8000>;
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d-cache-sets = <128>;
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d-cache-line-size = <64>;
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d-cache-block-size = <64>;
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next-level-cache = <&L2>;
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CPU0_intc: interrupt-controller {
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#interrupt-cells = <1>;
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interrupt-controller;
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compatible = "riscv,cpu-intc";
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};
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};
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CPU1: cpu@1 {
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device_type = "cpu";
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reg = <1>;
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status = "okay";
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compatible = "riscv";
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riscv,isa = "rv64imafdc";
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riscv,priv-major = <1>;
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riscv,priv-minor = <10>;
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mmu-type = "riscv,sv48";
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clock-frequency = <60000000>;
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i-cache-size = <0x8000>;
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i-cache-sets = <256>;
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i-cache-line-size = <64>;
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i-cache-block-size = <64>;
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d-cache-size = <0x8000>;
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d-cache-sets = <128>;
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d-cache-line-size = <64>;
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d-cache-block-size = <64>;
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next-level-cache = <&L2>;
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CPU1_intc: interrupt-controller {
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#interrupt-cells = <1>;
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interrupt-controller;
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compatible = "riscv,cpu-intc";
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};
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};
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CPU2: cpu@2 {
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device_type = "cpu";
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reg = <2>;
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status = "okay";
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compatible = "riscv";
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riscv,isa = "rv64imafdc";
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riscv,priv-major = <1>;
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riscv,priv-minor = <10>;
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mmu-type = "riscv,sv48";
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clock-frequency = <60000000>;
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i-cache-size = <0x8000>;
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i-cache-sets = <256>;
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i-cache-line-size = <64>;
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i-cache-block-size = <64>;
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d-cache-size = <0x8000>;
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d-cache-sets = <128>;
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d-cache-line-size = <64>;
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d-cache-block-size = <64>;
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next-level-cache = <&L2>;
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CPU2_intc: interrupt-controller {
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#interrupt-cells = <1>;
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interrupt-controller;
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compatible = "riscv,cpu-intc";
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};
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};
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CPU3: cpu@3 {
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device_type = "cpu";
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reg = <3>;
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status = "okay";
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compatible = "riscv";
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riscv,isa = "rv64imafdc";
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riscv,priv-major = <1>;
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riscv,priv-minor = <10>;
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mmu-type = "riscv,sv48";
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clock-frequency = <60000000>;
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i-cache-size = <0x8000>;
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i-cache-sets = <256>;
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i-cache-line-size = <64>;
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i-cache-block-size = <64>;
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d-cache-size = <0x8000>;
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d-cache-sets = <128>;
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d-cache-line-size = <64>;
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d-cache-block-size = <64>;
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next-level-cache = <&L2>;
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CPU3_intc: interrupt-controller {
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#interrupt-cells = <1>;
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interrupt-controller;
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compatible = "riscv,cpu-intc";
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};
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};
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};
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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compatible = "andestech,riscv-ae350-soc", "simple-bus";
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ranges;
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plic0: interrupt-controller@e4000000 {
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compatible = "riscv,plic0";
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reg = <0x00000000 0xe4000000 0x00000000 0x02000000>;
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interrupts-extended = < &CPU0_intc 11 &CPU0_intc 9
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&CPU1_intc 11 &CPU1_intc 9
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&CPU2_intc 11 &CPU2_intc 9
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&CPU3_intc 11 &CPU3_intc 9 >;
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interrupt-controller;
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#address-cells = <2>;
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#interrupt-cells = <2>;
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riscv,ndev = <71>;
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};
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plicsw: interrupt-controller@e6400000 {
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compatible = "andestech,plicsw";
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reg = <0x00000000 0xe6400000 0x00000000 0x00400000>;
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interrupts-extended = < &CPU0_intc 3
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&CPU1_intc 3
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&CPU2_intc 3
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&CPU3_intc 3 >;
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interrupt-controller;
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#address-cells = <2>;
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#interrupt-cells = <2>;
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};
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plmt0: plmt0@e6000000 {
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compatible = "andestech,plmt0";
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reg = <0x00000000 0xe6000000 0x00000000 0x00100000>;
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interrupts-extended = < &CPU0_intc 7
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&CPU1_intc 7
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&CPU2_intc 7
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&CPU3_intc 7 >;
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};
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wdt: watchdog@f0500000 {
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compatible = "andestech,atcwdt200";
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reg = <0x00000000 0xf0500000 0x00000000 0x00001000>;
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interrupts = <3 4>;
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interrupt-parent = <&plic0>;
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clock-frequency = <15000000>;
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};
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serial0: serial@f0300000 {
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compatible = "andestech,uart16550", "ns16550a";
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reg = <0x00000000 0xf0300000 0x00000000 0x00001000>;
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interrupts = <9 4>;
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interrupt-parent = <&plic0>;
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clock-frequency = <19660800>;
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current-speed = <38400>;
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reg-shift = <2>;
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reg-offset = <32>;
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reg-io-width = <4>;
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no-loopback-test = <1>;
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};
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smu: smu@f0100000 {
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compatible = "andestech,atcsmu";
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reg = <0x00000000 0xf0100000 0x00000000 0x00001000>;
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};
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};
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```
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