2 Commits

Author	SHA1	Message	Date
Lad Prabhakar	dea0922f86	platform: renesas/rzfive: Configure Local memory regions as part of root domain ... Renesas RZ/Five RISC-V SoC has Instruction local memory and Data local memory (ILM & DLM) mapped between region 0x30000 - 0x4FFFF. When a virtual address falls within this range, the MMU doesn't trigger a page fault; it assumes the virtual address is a physical address which can cause undesired behaviours for statically linked applications/libraries. To avoid this, add the ILM/DLM memory regions to the root domain region of the PMPU with permissions set to 0x0 for S/U modes so that any access to these regions gets blocked and for M-mode we grant full access (R/W/X). Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Anup Patel <anup@brainfault.org>	2023-01-23 11:29:03 +05:30
Lad Prabhakar	8b1617d13a	platform: generic: Add Renesas RZ/Five initial support ... This commit provides basic support for the Renesas RZ/Five (R9A07G043F) SoC. The RZ/Five microprocessor includes a single RISC-V CPU Core (Andes AX45MP) 1.0 GHz, 16-bit DDR3L/DDR4 interface. Supported interfaces include: - Gigabit Ethernet 2ch - CAN interface (CAN-FD) 2ch - USB 2.0 interface 2ch - SD interface 2ch - AD converter 2ch Useful links: ------------- Links: https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-mpus/rzfive-risc-v-general-purpose-microprocessors-risc-v-cpu-core-andes-ax45mp-single-10-ghz-2ch-gigabit-ethernet Links: http://www.andestech.com/en/products-solutions/andescore-processors/riscv-ax45mp/ Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Anup Patel <anup@brainfault.org>	2022-12-12 18:50:56 +05:30