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Author SHA1 Message Date
dramforeverandAnup Patel 187127fb89 lib: sbi: Fixup tinst for exceptions in sbi_misaligned_*() 
If there is an exception while emulating a misaligned load/store, fixup
uptrap.tinst before redirecting. Otherwise, HS-mode software may receive
an htinst describing the lbu/sb instruction that faulted during
emulation[1].

[1]: https://github.com/riscv-software-src/opensbi/issues/258

Signed-off-by: dramforever <dramforever@live.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
 2022-06-21 08:31:14 +05:30
dramforeverandAnup Patel 551c70c040 include: sbi: Add mtinst/htinst psuedoinstructions 
Add psuedoinstruction encodings written to mtinst/htinst for faults
caused by implicit memory access for VS-stage address translation

Signed-off-by: dramforever <dramforever@live.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
 2022-06-21 08:31:04 +05:30
dramforeverandAnup Patel adc3388d76 lib: sbi_trap: Redirect exception based on hedeleg 
HS-mode software can choose what exceptions to delegate to VS-mode using
the hedeleg CSR. Synthetic VS/VU-mode exceptions should also honor
hedeleg. They should be redirected to VS-mode if and only if delegated
by HS-mode.

Signed-off-by: dramforever <dramforever@live.com>
Reviewed-by: Xiang W <wxjstz@126.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
 2022-06-13 11:02:49 +05:30