Changes are made to support our FPGA evaluation board,
it has DDR memory(0xA0000000-0xB0000000).
* Adapt the config.mk to match FPGA evaluation board DDR memory address
* Since the RISC-V CPU core frequency of FPGA might change, so we use the
fixed TIMER frequency to measure the real CPU core frequency.
* And the UART baudrate has to set to 57600bps for Nuclei FPGA evaluation
board when CPU core frequency is about 8MHz, otherwise the UART input
will not work correctly.
Signed-off-by: Huaqi Fang <578567190@qq.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
