forked from Mirrors/opensbi
518e85cccb
Changes are made to support our FPGA evaluation board, it has DDR memory(0xA0000000-0xB0000000). * Adapt the config.mk to match FPGA evaluation board DDR memory address * Since the RISC-V CPU core frequency of FPGA might change, so we use the fixed TIMER frequency to measure the real CPU core frequency. * And the UART baudrate has to set to 57600bps for Nuclei FPGA evaluation board when CPU core frequency is about 8MHz, otherwise the UART input will not work correctly. Signed-off-by: Huaqi Fang <578567190@qq.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
31 lines
606 B
Makefile
31 lines
606 B
Makefile
#
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# SPDX-License-Identifier: BSD-2-Clause
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#
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# Copyright (c) 2020 Nuclei Corporation or its affiliates.
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#
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# Authors:
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# lujun <lujun@nucleisys.com>
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# hqfang <578567190@qq.com>
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#
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# Compiler flags
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platform-cppflags-y =
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platform-cflags-y =
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platform-asflags-y =
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platform-ldflags-y =
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# Command for platform specific "make run"
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platform-runcmd = xl_spike \
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$(build_dir)/platform/nuclei/ux600/firmware/fw_payload.elf
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# Blobs to build
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FW_TEXT_START=0xA0000000
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FW_DYNAMIC=y
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FW_JUMP=y
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FW_JUMP_ADDR=0xA0200000
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FW_JUMP_FDT_ADDR=0xA8000000
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FW_PAYLOAD=y
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FW_PAYLOAD_OFFSET=0x200000
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FW_PAYLOAD_FDT_ADDR=0xA8000000
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