Multi-core communication via memory requires the addition of a barrier instructions to ensure cache coherency. Signed-off-by: Xiang Wang <wxjstz@126.com>
Writable code section can cause some security problems, so move _boot_hart_done to the data section Signed-off-by: Xiang Wang <wxjstz@126.com>
Signed-off-by: Xiang Wang <wxjstz@126.com>